Common use of Endpoint Descriptor Description Clause in Contracts

Endpoint Descriptor Description. Endpoint Descriptors (ED) are linked in lists that are processed by the HC. An ED is linked to a next ED when the NextED field is nonzero. When the Host Controller accesses an ED, it checks the sKip and the Halted bits to determine if any further processing of the ED is allowed. If either bit is set, then the Host Controller advances to the next ED on the list. If neither the sKip nor the Halted bit is set, then the Host Controller compares HeadP to TailP. If they are not the same, then the TD pointed to by HeadP defines a buffer to/from which the Host Controller will transfer a data packet. This linking convention assumes that the Host Controller Driver queues to the ‘tail’ of the TD queue. It does this by linking a new TD to the TD pointed to by TailP and then updating TailP to point to the TD just added. When processing of a TD is complete, the Host Controller ‘retires’ the TD by unlinking it from the ED and linking it to the Done Queue. When a TD is unlinked, NextTD of the TD is copied to HeadP of the ED. The sKip bit is set and cleared by the Host Controller Driver when it wants the Host Controller to skip processing of the endpoint. This may be necessary when the Host Controller Driver must modify the value of HeadP and the overhead of removing the ED from its list is prohibitive. The Halted bit is set by the Host Controller when it encounters an error in processing a TD. When the TD in error is moved to the Done Queue, the Host Controller updates HeadP and sets the Halted bit, causing the Host Controller to skip the ED until Halted is cleared. The Host Controller Driver clears the Halted bit when the error condition has been corrected and transfers to/from the endpoint should resume. The Host Controller Driver should not write to HeadP/toggleCarry/Halted unless Halted is set, sKip is set, or the ED has been removed from the list. When TDs are queued to an ED, the Host Controller processes the TDs asynchronously with respect to processing by the host processor. Therefore, if the Host Controller Driver needs to alter the TD queue other than appending to the queue, it must stop the Host Controller from processing the TD queue for the endpoint so that changes can be made. The nominal mechanisms for stopping TD processing are for the Host Controller Driver to remove the ED from the list or to set the sKip bit in the ED. When the D field of an ED is 10b (IN), the Host Controller may issue an IN token to the specified endpoint after it determines that HeadP and TailP are not the same. This indicates that a buffer exists for the data and that input of the endpoint data may occur in parallel with the HC’s access of the TD which defines the memory buffer. Since an ED must be aligned to a 16-byte boundary, the Host Controller only uses the upper 28 bits of Dword3 as a pointer to the next ED. TailP and HeadP point to TDs which may be either 16- or 32- byte aligned. The Host Controller uses only the upper 28 bits of Dword1 and Dword2 to point to a 16-byte aligned TD (F = 0). If HeadP and TailP point to a TD that must be 32-byte aligned (F = 1), then bit 4 of these Dwords must be 0.

Endpoint Descriptor Description. Endpoint Descriptors (ED) are linked in lists that are processed by the HC. An ED is linked to a next ED when the NextED field is nonzero. When the Host Controller accesses an ED, it checks the sKip and the Halted bits to determine if any further processing of the ED is allowed. If either bit is set, then the Host Controller advances to the next ED on the list. If neither the sKip nor the Halted bit is set, then the Host Controller compares HeadP to TailP. If they are not the same, then the TD pointed to by HeadP defines a buffer to/from which the Host Controller will transfer a data packet. This linking convention assumes that the Host Controller Driver queues to the ‘tail’ of the TD queue. It does this by linking a new TD to the TD pointed to by TailP and then updating TailP to point to the TD just added. When processing of a TD is complete, the Host Controller ‘retires’ the TD by unlinking it from the ED and linking it to the Done Queue. When a TD is unlinked, NextTD of the TD is copied to HeadP of the ED. The sKip bit is set and cleared by the Host Controller Driver when it wants the Host Controller to skip processing of the endpoint. This may be necessary when the Host Controller Driver must modify the value of HeadP and the overhead of removing the ED from its list is prohibitive. The Halted bit is set by the Host Controller when it encounters an error in processing a TD. When the TD in error is moved to the Done Queue, the Host Controller updates HeadP and sets the Halted bit, causing the Host Controller to skip the ED until Halted is cleared. The Host Controller Driver clears the Halted bit when the error condition has been corrected and transfers to/from the endpoint should resume. The Host Controller Driver should not write to HeadP/toggleCarry/Halted unless Halted is set, sKip is set, or the ED has been removed from the list. When TDs are queued to an ED, the Host Controller processes the TDs asynchronously with respect to processing by the host processor. Therefore, if the Host Controller Driver needs to alter the TD queue other than appending to the queue, it must stop the Host Controller from processing the TD queue for the endpoint so that changes can be made. The nominal mechanisms for stopping TD processing are for the Host Controller Driver to remove the ED from the list or to set the sKip bit in the ED. When the D field of an ED is 10b (IN), the Host Controller may issue an IN token to the specified endpoint after it determines that HeadP and TailP are not the same. This indicates that a buffer exists for the data and that input of the endpoint data may occur in parallel with the HC’s access of the TD which defines the memory buffer. Since an ED must be aligned to a 16-byte boundary, the Host Controller only uses the upper 28 bits of Dword3 as a pointer to the next ED. TailP and HeadP point to TDs which may be either 16- or 32- 32-byte aligned. The Host Controller uses only the upper 28 bits of Dword1 and Dword2 to point to a 16-byte aligned TD (F = 0). If HeadP and TailP point to a TD that must be 32-byte aligned (F = 1), then bit 4 of these Dwords must be 0.