Common use of Endpoint List Processing Clause in Contracts

Endpoint List Processing. The Host Controller schedules transfers to endpoints on USB based on the structure of the four endpoint lists: bulk, control, interrupt, and isochronous. For bulk and control, the Host Controller maintains a software- accessible pointer to the head of the list. For interrupt, 32 list heads are kept in memory with a list selected each frame. The isochronous list is linked to the end of all of the interrupt lists. In addition to the head pointers, the Host Controller maintains three software-accessible pointers to the current ED for control, bulk, and an additional pointer that is used for both periodic lists (interrupt and isochronous.) The Host Controller selects a list to process based on a priority algorithm. At the beginning of each frame, processing of the control and bulk list has priority until the HcFmRemaining counts down to the value in HcPeriodicStart. At that point, processing of the periodic lists has priority over control/bulk processing until either periodic list processing is complete or the frame time expires. While control and bulk have priority, the Host Controller alternates processing of EDs on each of the lists. The setting of the Control Bulk Ratio field in HcControl determines the ratio of the number of control to bulk transactions that will be attempted. If CB is set to 00b, then the Host Controller allows one bulk transaction for each control transaction. If CB = 11b, then the Host Controller allows one bulk transition after every 4 control transactions. If either the control or bulk lists is empty, then 100% of the control/bulk time is allocated to the list that is not empty. The control and bulk lists are considered empty if either no EDs are linked to the list (the head pointer in the Host Controller contains a zero) or if all the TD queues of the EDs on the list are empty. To detect this empty condition, the Host Controller maintains two bits: control-filled (CF) and bulk-filled (BF) in the HcCommandStatus register. When the Host Controller starts processing at the head of the control or bulk list, it clears the corresponding filled bit. When the Host Controller finds an ED in the control or bulk list with a TD to be processed, it sets the corresponding filled bit. When the Host Controller reaches the end of the list, it checks the filled bit. If it is zero, then the list is empty and processing of the list stops. When the Host Controller Driver makes an addition to either the control or bulk lists, it must write to the corresponding filled bit to ensure that the Host Controller continues to process the list.