JOINT DEVELOPMENT PROJECT AGREEMENT for 32nm BULK-INDUSTRY STANDARD SEMICONDUCTOR PROCESS TECHNOLOGY with INTERNATIONAL BUSINESS MACHINES CORP. dated DECEMBER 15, 2006

Exhibit 4.11.16

Confidential Treatment Requested
The portions of this document marked by “XXXXXX” have been omitted pursuant to a request for confidential
treatment and have been filed separately with the Securities and Exchange Commission

Final		32nm Bulk-Industry Standard Semiconductor Process Technology

JOINT DEVELOPMENT PROJECT AGREEMENT

for

32nm BULK-INDUSTRY STANDARD SEMICONDUCTOR PROCESS TECHNOLOGY

with

INTERNATIONAL BUSINESS MACHINES CORP.

dated

DECEMBER 15, 2006

IBM CONFIDENTIAL	1	Joint Development Project Agreement

Final		32nm Bulk-Industry Standard Semiconductor Process Technology

This Joint Development Project Agreement for 32nm Bulk-Industry Standard Semiconductor Process Technology (“Project Agreement”) is made effective as of December 15, 2006 (the “Effective Date”) by and between International Business Machines Corporation (“IBM”), incorporated under the laws of the State of New York, U.S.A. and having an office for the transaction of business at ▇▇▇▇ ▇▇▇▇▇ ▇▇, ▇▇▇▇▇▇▇▇ ▇▇▇▇▇▇▇▇, ▇▇ ▇▇▇▇▇, U.S.A, and all Participating Parties.

WHEREAS, IBM has developed and continues to develop leading edge semiconductor manufacturing processes technology and wishes to continue and/or expand such technology development in conjunction with the Participating Parties;

WHEREAS, the Participating Parties seek to undertake such technology development with each other and with IBM based upon the terms and conditions provided in this Project Agreement (including the Master Terms);

WHEREAS, each Participating Party and IBM will also supplement this Project Agreement (including the Master Terms) by executing a Participation Agreement that provides certain supplemental terms and conditions that only govern between IBM and such Participating Party; and

WHEREAS, through the use of complementary skills and know-how the Parties desire to achieve resource efficiencies and cost savings, and reduce the technical risk associated with the development of the subject technology in order to complete development of and utilize leading edge technologies sooner than would be possible with any of the Parties acting independently.

NOW THEREFORE, in consideration of the premises and mutual covenants contained herein, as well as for other good and valuable consideration, the receipt and sufficiency of which is hereby acknowledged, the Parties agree as follows.

1. Additional Definitions. Unless expressly defined and used with an initial capital letter in the Master Terms (as defined below) or the rest of this Project Agreement, words shall have their normally accepted meanings. The following terms shall have the meanings ascribed to them:

“Background Know-How Exclusions” is defined in Section 4(b).

“Bulk CMOS” means CMOS semiconductor manufacturing technology carried out on a wafer that is not an SOI Wafer.

“Bulk CMOS Integrated Circuit” means an Integrated Circuit fabricated utilizing a Bulk CMOS manufacturing process.

“Chip Design(s)” means any design of one or more Integrated Circuits and/or Semiconductor Products, including (by way of example and not limitation) random access memory (RAM)s, read only memory (ROM)s, microprocessors, application specific Integrated Circuits (ASICs) and other logic designs, and analog circuitry; provided,

IBM CONFIDENTIAL	2	Joint Development Project Agreement

Final		32nm Bulk-Industry Standard Semiconductor Process Technology

however, that “Chip Designs” shall not include (i) alignment marks or test structures and associated layout and data used in the Development Projects for process development, (ii) process kerf test structures, layout, and data of the test chip(s) (including SRAM or ROM macro cells) as well as such test chips themselves used for the development work of the Development Projects unless any of the foregoing items are specifically excluded (for clarity, to “specifically exclude” such an item means it is included in the definition of Chip Design), or (iii) other product designs as mutually agreed by the Parties to be used as qualification vehicles in the Development Projects unless specifically excluded (for clarity, to “specifically exclude” a product design means it is included in the definition of Chip Design), or (iv) ESD protection devices as used in the project Test Sites and ESD groundrules and models as defined in the Documentation. For the avoidance of doubt, all of (i) through (iv) above shall be treated as Specific Results to the extent utilized in a Development Project.

“32nm Bulk CMOS” also known as “32nm Industry Standard CMOS” means the next major lithography generation Bulk CMOS logic fabrication process technology for 300mm wafers below 45nm, with the target objectives set forth in Exhibit A, attached hereto.

“Development Project” means the technology development project and any sub-projects identified in Exhibit A to this Project Agreement.

“Effective Date” means the date set forth in the preamble of this Project Agreement.

“L1” means yield, process and reliability demonstration on an integrated process Test Site (all JEDEC qualification tests & preliminary functional stress). Qualification criteria will be mutually reviewed for consistency with application requirements. Reliability stresses are as per industry standard criteria and specifications.

“Mask Fabrication and Photoresist Technology” means any process, procedure, Proprietary Tools, Third Party tools, or hardware tool used in the fabrication of photomasks, as well as the photomasks themselves, and/or the formulation and/or manufacture of photoresist; provided, however, that “Mask Fabrication and Photoresist Technology” shall not include Lithography.

“Master Terms” means the Master IBM Joint Development Terms and Conditions December 15, 2006 version.

“Manufacturing Apparatus” means semiconductor wafer fabrication equipment, flat-panel display fabrication equipment and wafer inspection equipment or components primarily designed for use in such equipment, including, without limitation, software, firmware, microcode or drivers used to cause such equipment to perform its intended function, whether or not such software, firmware, microcode, or drivers are shipped with such equipment or installed separately. “Participating Party Qualification” also known as the “Participating Party L2” means the successful completion of foundry standard stress on a product and/or a product like vehicle with mixed signal, digital, and SRAM elements

IBM CONFIDENTIAL	3	Joint Development Project Agreement

Final		32nm Bulk-Industry Standard Semiconductor Process Technology

and with manufacturing process routing defined, in the Participating Party’s manufacturing facility for 300mm Wafers.

“Party” means IBM and each Participating Party in the Development Project.

“Project Agreement” means the terms and conditions of this Joint Development Project Agreement for 32nm Bulk-Industry Standard Semiconductor Process Technology dated December 15, 2006, together with (i) any exhibits, attachments and appendices hereto, and (ii) the “Participating Party Notification” for each Participating Party.

“Project Term” is defined in Section 6.

“Qualification” also known as “L2” and means the successful completion of foundry standard stress (i.e. a stress which is based upon industry standard criteria and specifications) on a product and/or a product like vehicle with mixed signal, digital, and SRAM elements and with manufacturing process routing defined, in the IBM manufacturing line for 300mm Wafers and consistent with the Strategic Technology Objectives as set forth in Exhibit A.

“Silicon-Germanium Technology” or “SiGe Technology” means semiconductor fabrication processes and design techniques incorporating silicon and germanium layers, including those processes and design techniques for use in HEMTs, photodetectors, HBTs or any other applications of bipolar transistors, provided, however, “SiGe Technology” shall not include strained silicon channel MOSFET or any mobility enhancement techniques for FETs carried out on high performance Integrated Circuit wafers.

“Silicon-On-Insulator Wafer” or “SOI Wafer” means a single-crystal silicon wafer bearing a horizontally-disposed isolating silicon dioxide (SiO₂) layer, in turn bearing a single-crystal silicon layer or a polysilicon layer, which is separated from the underlying silicon by the silicon dioxide layer and in which one or more active or passive integrated circuit structures are formed.

“SOI Information” means any and all process methods, steps, and structures created on SOI Wafers and not on Bulk CMOS Integrated Circuits.

“Specific Results Exclusions” is defined in Section 3(a).

2. IBM Development Facilities; Agreement Structure; Relationship to Other Documents.

(a) The Parties shall primarily utilize the IBM Development Facilities for the Development Project.

(b) The terms and conditions of the Master Terms are incorporated into this Project Agreement by reference as if fully set forth herein.

IBM CONFIDENTIAL	4	Joint Development Project Agreement

Final		32nm Bulk-Industry Standard Semiconductor Process Technology

(c) IBM shall promptly notify existing Participating Parties of the addition of a new Participating Party to and the withdrawal/ removal of an existing Participating Party from the Development Project. In the case of a new Participating Party, IBM shall complete such notification by distributing copies of the signed “Participating Party Notification”, which provides certain details about the new Participating Party (e.g. the first day of its participation, Designated Executive, Project Leader and Notice Addresses), and memorializes the new Participating Party’s contractual privity with the other Participating Parties.

(d) The Party’s respective ownership, disclosure, and/or license rights as to the Specific Results and Background Know-How are set forth in that Party’s Participation Agreement and this Project Agreement (including the Master Terms).

(e) For the Development Project, the Parties will strive to utilize consumables (including, but not limited to, photoresist) in the Development Project that will be available to the Parties from commercial suppliers. However, if a consumable proposed by IBM is an IBM proprietary consumable, the IBM Project Leader will notify the Participating Parties of such proposed selection, specifying the respects in which the consumable is IBM proprietary. In addition, within thirty (30) days of such proposed selection IBM will inform the Third Party supplier of such IBM proprietary consumable that if such supplier is chosen by IBM, such supplier may provide such proprietary consumable to the Participating Parties irrespective of any IBM imposed restriction or proprietary rights that might otherwise exist. If such supplier refuses to sell the proprietary consumable to Participating Parties or IBM and the Participating Parties reasonably believe that such supplier will not sell to Participating Parties, then IBM shall either enable Participating Parties to purchase such consumable from another source or select another consumable prior to the applicable Qualification.

3.		Scope of Development Project.

(a) As part of the Development Project, the Parties shall jointly develop semiconductor manufacturing process technology based on an industry standard technology roadmap that meets the requirements set forth as “Strategic Technology Objectives” in Exhibit A in accordance with the schedule set forth on Exhibit B (the “Development Schedule”). The Parties shall create the Documentation identified on Exhibit C for the Development Project. For the avoidance of doubt, the Development Project shall not include the development of the following “Specific Results Exclusions”: i) Proprietary Tools, ii) Packaging Technology, iii) Mask Fabrication and Photoresist Technology, iv) Memory, v) SiGe Technology, vi) SOI Information, and vii) Chip Designs. The Parties are not obligated to exchange any updates to the Specific Results after the Project Term.

(b) The Parties agree that Exhibit A also sets forth the current, as of the Effective Date, technology implementation options for the Development Project. The Parties shall work together to evaluate the various options available, including individual Process Module feasibility, integration, characterization, and qualification. The goal of such evaluation is to agree on an integrated process technology that meets the Strategic Technology

IBM CONFIDENTIAL	5	Joint Development Project Agreement

REDACTED		CONFIDENTIAL TREATMENT REQUESTED The portions of this document marked by “XXXXX” have been omitted and are filed separately with the Securities and Exchange Commission.

Final		32nm Bulk-Industry Standard Semiconductor Process Technology

Objectives. If the Project Leaders are unable to agree on a particular Process Module to be developed, or should they disagree as to continued development of a Process Module that was previously selected, the Process Module preferred by IBM shall be pursued in the Development Project, provided it is consistent with foundry industry marketplace requirements and the standard baseline Bulk CMOS process for such fabrication process generation. Any Participating Party may escalate the failure to agree through the procedures set forth in Section 18.3 of the Master Terms. In the event that a Party proposes a Process Module or replacement Process Module that does not get selected after escalation, then such Party shall have the right, subject to the remaining terms and conditions of the Agreement, to proceed with such development outside the performance of the Development Projects.

4.		Information Transfers.

(a) As referenced in Section 7.3 of the Master Terms, the “Confidentiality Period” is from the Effective Date until XXXXXX after the date set forth on Exhibit B (as of the Effective Date) for the applicable Qualification.

(b) As referenced in the Master Terms, the “Background Know How Exclusions” for purposes of the Development Project are: i) Proprietary Tools, ii) Packaging Technology, iii) Mask Fabrication and Photoresist Technology, iv) Memory, v) SiGe Technology, vi) SOI Information, and vii) Chip Designs.

(c) In addition to the disclosure rights of a Participating Party pursuant to Section 7 and license rights in Section 8 of the Master Terms, each Participating Party has the following rights to disclose portions of Specific Results and/or Background Know-How, solely for the purpose of exercising its rights under the Agreement:

		1. To contractors, suppliers, and consultants (and, for clarity, Subsidiaries of such Participating Party acting in any of the foregoing capacities) as may be reasonably necessary for Participating Party to manufacture Integrated Circuits and Semiconductor Products. By way of example and not limitation, examples of the general types of information the Parties agree are “reasonably necessary” for disclosure to such contractors, suppliers, and consultants are as follows:
		XXXXXX
		2. To customers (including companies providing design services to such customers), library/IP creators, Electronic Design Automation (“EDA”) vendors, consultants (such consultants including design service providers, integrated circuit designers, and external subcontractors), (and, for clarity, Subsidiaries of a Participating Party acting in any of the foregoing capacities) (collectively, “Customers/Designers”) as may be reasonably necessary to enable the design and sale of Integrated Circuits or Semiconductor Products to such customers by Participating Party. By way of example and not limitation, examples of the general types of information the Parties

IBM CONFIDENTIAL	6	Joint Development Project Agreement

REDACTED		CONFIDENTIAL TREATMENT REQUESTED The portions of this document marked by “XXXXX” have been omitted and are filed separately with the Securities and Exchange Commission.

Final		32nm Bulk-Industry Standard Semiconductor Process Technology

		agree are “reasonably necessary” for disclosure to some or all Customers/Designers are as follows:
		XXXXXX
		This Section 4(c)2 also includes the right to sublicense (as set forth in Section 8.5 of the Master Terms) to EDA vendors and circuit design or library providers where such sublicense is for the benefit of the Participating Party’s foundry business in connection with the manufacture and sale of wafers containing Integrated Circuits, acknowledging that such Third Parties may license for their own benefit the resultant EDA software and/or cores or IP blocks to Customers/Designers.
		This Section 4(c)2 also includes the right to disclose to a Participating Party’s customers as may be reasonably necessary, solely for the purpose of enabling the Participating Party to develop Derivative Technology for the manufacture of Integrated Circuits or Semiconductor Products solely for such customer and to manufacture Integrated Circuits or Semiconductor Products for such customer. The resultant Derivative Technology may be used by the Participating Party to manufacture Integrated Circuits or Semiconductor Products for future customers, but such future customers will not get any access to any of the Specific Results and/or Background Know-How, except as otherwise set forth in this Section 4.

Disclosures pursuant to this Section 4(c) will not be made without a written agreement between the Participating Party and the recipient Third Party. Such written agreements shall be subject to the following:

	(a)		such agreements must obligate the recipient to utilize the disclosed information solely for the benefit of the discloser and for no other purpose, and solely in furtherance of the purposes set forth in this Section 4; and
	(b)		such disclosures shall be subject to confidentiality terms and conditions that are the same or substantially similar to those set forth in this Agreement, and at a minimum must have a confidentiality term that is no shorter than XXXXXX.

5.		Tool Vendor Confidential Information.

Notwithstanding anything to the contrary in Section 4 of this Project Agreement, Section 3.6 of the Master Terms or the rest of the Agreement, the Parties recognize that IBM is working with certain Third Party tool vendors to develop, among other things, Background Know-How which may include Third Party tool vendor confidential information (“Tool Vendor Confidential Information”), and agree that (a) IBM may elect to introduce certain Tool Vendor Confidential Information into the Development Project as Background Know-How, and (b) the Specific Results may include such Tool Vendor Confidential Information. If IBM elects to so introduce such Tool Vendor Confidential

IBM CONFIDENTIAL	7	Joint Development Project Agreement

REDACTED		CONFIDENTIAL TREATMENT REQUESTED The portions of this document marked by “XXXXX” have been omitted and are filed separately with the Securities and Exchange Commission.

Final		32nm Bulk-Industry Standard Semiconductor Process Technology

Information, IBM shall identify such information and the following terms apply to such information:

Each Participating Party is authorized to disclose or sublicense to any of its business units and/or Subsidiaries the Tool Vendor Confidential Information; provided, however, that such business unit and/or Subsidiary is not in a business, nor has announced plans to be in, or to acquire, a business that manufactures, sells, or distributes Manufacturing Apparatus. If Participating Party wishes to obtain additional license rights to such Tool Vendor Confidential Information, then Participating Party must negotiate additional rights with such Third Party tool vendor. The obligations of confidentiality with respect to any disclosure to a Participating Party pursuant to this Section 5 shall terminate ten (10) years after disclosure by IBM, unless otherwise agreed in writing between such Third Party and the Participating Party, with written notification to IBM. Participating Party shall require that each such business unit and/or Subsidiary agree to maintain such Tool Vendor Confidential Information confidential on terms at least as restrictive as contained in this Agreement including this Section 5.

(a) This Project Agreement is in effect from the Effective Date and, unless terminated as set forth in the Agreement (including Section 12 of the Master Terms), remains in force until XXXXXX (the “Project Term”); provided, however, the Management Committee may extend the Project Term until XXXXXX in accordance with Section 18.15 of the Master Terms without the need for the Parties to execute a written amendment to this Project Agreement. For clarity, a Participating Party may, as specified in its Participation Agreement, participate in the Development Project for all or a portion of the Project Term.

(b) The Project Term may only be extended beyond XXXXXX (i) as to all Parties, by the mutual agreement of all Parties, or (ii) as to certain Parties, by mutual agreement of such Parties. Each Party who agrees to extend the Project Term beyond XXXXXX shall memorialize its agreement to participate in such extensions by amending its Participation Agreement with IBM. IBM shall update the Project Database to reflect such Project Term extension.

(c) The following Sections of this Project Agreement survive and continue to bind the Parties and their legal representatives, successors and assigns after the expiration or termination of this Project Agreement: 1, 2(b), 2(d), 4, 5, 6(c), 6(d) and 8. In addition, certain provisions of the Master Terms and a Participating Party’s Participation Agreement survive, as detailed in each agreement, respectively.

(d) Notwithstanding any provision in this Project Agreement to the contrary, if a non-breaching Party is authorized to terminate all licenses and disclosure rights granted to a breaching Party pursuant to Section 12.6 of the Master Terms, then such non-breaching

IBM CONFIDENTIAL	8	Joint Development Project Agreement

REDACTED		CONFIDENTIAL TREATMENT REQUESTED The portions of this document marked by “XXXXX” have been omitted and are filed separately with the Securities and Exchange Commission.

Final		32nm Bulk-Industry Standard Semiconductor Process Technology

Party is also authorized to terminate all license and disclosure rights it granted to that breaching party pursuant to Section 4 of this Project Agreement.

7. Management of the Development Project; Notice. Each Participating Party shall promptly provide a Management Committee Member, a Project Leader, a Technical Coordinator, a Designated Executive, and a Notice Address for the Development Project.

The IBM Management Committee Member, IBM Project Leader, IBM Technical Coordinator, Designated Executive, and the Notice Address are as follows:

          XXXXXX

Any Party may change its respective appointments and addresses by written notice to the IBM Project Leader who will update the Project Database within seven (7) business days after notification. No such change is effective until reflected in the Project Database .

8. Limitation Amount. As referenced in Section 17 (Limitation of Liability) of the Master Terms, the Limitation Amount for this Development Project is XXXXXX.

[REMAINDER OF PAGE INTENTIONALLY LEFT BLANK]

IBM CONFIDENTIAL	9	Joint Development Project Agreement

Final		32nm Bulk-Industry Standard Semiconductor Process Technology

IN WITNESS WHEREOF, IBM has caused this Project Agreement to be executed by its duly authorized representatives as of the Effective Date, signifying its agreement to this Project Agreement with all Participating Parties.

International Business Machines Corporation

By: /s/▇▇▇▇▇▇ ▇. ▇▇▇▇▇▇▇
Name: ▇▇▇▇▇▇ ▇. ▇▇▇▇▇▇▇
Title: GM Technology Collaboration Solutions

Date:12/15/06

IBM CONFIDENTIAL	10	Joint Development Project Agreement

Final		32nm Bulk-Industry Standard Semiconductor Process Technology

EXHIBIT A: TECHNICAL OBJECTIVES

EXHIBIT B: DEVELOPMENT SCHEDULE

EXHIBIT C: DOCUMENTATION

IBM CONFIDENTIAL	11	Joint Development Project Agreement

REDACTED		CONFIDENTIAL TREATMENT REQUESTED The portions of this document marked by “XXXXX” have been omitted and are filed separately with the Securities and Exchange Commission.

Final		32nm Bulk-Industry Standard Semiconductor Process Technology

EXHIBIT A

TECHNICAL OBJECTIVES

XXXXXX

IBM CONFIDENTIAL	12	Joint Development Project Agreement

REDACTED		CONFIDENTIAL TREATMENT REQUESTED The portions of this document marked by “XXXXX” have been omitted and are filed separately with the Securities and Exchange Commission.

Final		32nm Bulk-Industry Standard Semiconductor Process Technology

EXHIBIT B

DEVELOPMENT SCHEDULE

XXXXXX

IBM CONFIDENTIAL	13	Joint Development Project Agreement

REDACTED		CONFIDENTIAL TREATMENT REQUESTED The portions of this document marked by “XXXXX” have been omitted and are filed separately with the Securities and Exchange Commission.

Final		32nm Bulk-Industry Standard Semiconductor Process Technology

EXHIBIT C

DOCUMENTATION

XXXXXX

IBM CONFIDENTIAL	14	Joint Development Project Agreement