SECOND AMENDED AND RESTATED [***] SUPPLY AGREEMENT

EXHIBIT 10.49

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This SECOND AMENDED AND RESTATED [***] SUPPLY AGREEMENT (this “Agreement”) is entered into as of February 10, 2017 but made effective as of the Original Effective Date by and between Intel Corporation, a Delaware corporation (“Intel”), Micron Semiconductor Asia Pte. Ltd., a Singapore corporation (“MSA”) and Micron Technology, Inc., a Delaware corporation (“MTI” and, together with MSA, collectively, “Micron”). This Agreement amends and restates, in its entirety, the Amended and Restated [***] Supply Agreement dated as of September 1, 2015 (the “First Amended and Restated [***] Supply Agreement), which amended and restated, in its entirety, the [***] Wafer Supply Agreement (as amended prior to September 1, 2015, the “Original Agreement”), dated as of January 31, 2014 (the “Original Effective Date”), all by and between Intel and Micron. Each of Intel, MSA and MTI may be referred to herein individually as a “Party” and collectively as the “Parties.”

RECITALS

A. In connection with the execution of the Original Agreement, Micron and Intel entered into a [***] Letter Agreement (the “[***] Letter Agreement”) pursuant to which MSA agreed to use commercially reasonable efforts to convert existing capacity or add incremental capacity at the Singapore Fab to manufacture wafers utilizing the [***] Process Technology Node and Intel agreed to cooperate with, and use commercially reasonable efforts to assist, Micron in qualifying such [***] Process Technology Node at such facilities.

B. If such manufacturing conversion or addition occur, and if Intel complies with Sections 2.1 and 3 of the [***] Letter Agreement, MSA would manufacture NAND Flash Memory Wafers utilizing the [***] Process Technology Node at its Singapore Fab and supply Probed Wafers utilizing the [***] Process Technology Node to Intel in accordance with the terms and subject to the conditions set forth in this Agreement.

C. In connection with the execution of the First Amended and Restated [***] Supply Agreement, Micron and Intel entered into a [***] Letter Agreement (the “[***] Letter Agreement”) pursuant to which MSA agreed, subject to the conditions therein, to use commercially reasonable efforts to convert existing capacity or add incremental capacity at the Singapore Fab to manufacture wafers utilizing the [***] Process Technology Node and Intel agreed to cooperate with, and use commercially reasonable efforts to assist, Micron in qualifying such [***] Process Technology Node at such facilities.

D. If such manufacturing conversion or addition occur, and if Intel complies with Sections 1.2, 1.3 and 1.4 of the [***] Letter Agreement, MSA would manufacture NAND Flash Memory Wafers utilizing the [***] Process Technology Node at its Singapore manufacturing facilities and supply Probed Wafers utilizing the [***] Process Technology Node to Intel, in accordance with the terms and subject to the conditions set forth in this Agreement.

E. Intel agrees to purchase Probed Wafers, in accordance with the terms and subject to the conditions set forth in this Agreement.

F. Under the Amended and Restated Deposit Agreement entered into as of February 10, 2017, by and among Intel and MTI (the “Deposit Agreement”), Intel agreed to make with Micron a refundable deposit against Intel’s payment obligations in accordance with Section 2.3 of the Deposit Agreement.

AGREEMENT

NOW, THEREFORE, for good and valuable consideration, the receipt and sufficiency of which are hereby acknowledged, the Parties intending to be legally bound do hereby agree as follows:

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ARTICLE 1

DEFINITIONS; CERTAIN INTERPRETIVE MATTERS

1.1 Definitions. In addition to the terms defined elsewhere in this Agreement, capitalized terms used in this Agreement shall have the respective meanings set forth in Exhibit A.

1.2 Certain Interpretive Matters.

(a) Unless the context requires otherwise, (i) all references to Sections, Articles, Recitals, Exhibits or Schedules are to Sections, Articles, Recitals, Exhibits or Schedules of or to this Agreement; (ii) each of the Schedules will apply only to the corresponding Section or subsection of this Agreement; (iii) words in the singular include the plural and vice versa; (iv) the term “including” means “including without limitation”; and (v) the terms “herein,” “hereof,” “hereunder” and words of similar import shall mean references to this Agreement as a whole and not to any individual Section or portion hereof. All references to $ or dollar amounts will be to lawful currency of the United States of America. All references to “day” or “days” will mean calendar days and all references to “quarter(ly)”, “month(ly)” or “year(ly)” will mean calendar quarter, calendar month or calendar year, respectively.

(b) No provision of this Agreement will be interpreted in favor of, or against, any of the Parties by reason of the extent to which any such Party or its counsel participated in the drafting thereof or by reason of the extent to which any such provision is inconsistent with any prior draft of this Agreement or such provision.

ARTICLE 2

GENERAL OBLIGATIONS

2.1 Supply and Purchase. Subject to the terms and conditions of this Agreement, Micron will supply to Intel, and Intel will purchase from Micron, Probed Wafers as set forth in this Section 2.1; provided that (i) with respect to Probed Wafers manufactured utilizing the [***] Process Technology Node, the manufacturing conversion or addition described in the [***] Letter Agreement has occurred and that Intel complies with Sections 2.1 and 3 of the [***] Letter Agreement and (ii) with respect to Probed Wafers manufactured utilizing the [***] Process Technology Node, the manufacturing conversion or addition described in the [***] Letter Agreement has occurred and that Intel complies with Sections 1.2, 1.3 and 1.4 of the [***] Letter Agreement. For the avoidance of doubt, the foregoing conditions with respect to the Intel obligations may be waived by Micron it its sole discretion.

(a) Pre-Qualified Probed Wafers.

(i) [***]. Beginning on the [***] Design ID Ready Date and continuing until the end of the Term, [***] of any [***] Pre-Qualified Probed Wafer starts (the “[***] Pre-Qualified Probed Wafer Commitment”).

(ii) [***]. Beginning on the [***] Design ID Ready Date and continuing until the end of the Term, [***] of any [***] Pre-Qualified Probed Wafer starts (the “[***] Pre-Qualified Probed Wafer Commitment” and together with the [***] Pre-Qualified Probed Wafer Commitment, the “Pre-Qualified Probed Wafer Commitment”).

(b) Qualified Probed Wafers. In each consecutive twelve-month period during the period commencing on the Start Date and ending at the end of the Term (each, an “Order Year”), but subject to the limits in this Section 2.1 and Section 3.1, [***] Qualified Probed Wafers spread over the applicable Order Year in accordance with Section 3.1 (the “Qualified Probed Wafer Commitment”).

(i) [***]. If during any week beginning [***] before the expected [***] Initial Joint Qualification Release and ending [***] after the [***] Initial Joint Qualification Release, the quantity of NAND Flash Memory Wafers utilizing the [***] Process Technology Node that is started, that if completed after [***] Initial Joint Qualification Release would be designated as [***] Qualified Probed Wafers, is less than [***], Micron will reallocate the actual NAND Flash Memory Wafer starts utilizing the [***] Process Technology Node to target [***] for [***]. The foregoing measures shall be in addition to those measures that may be required of Micron under Section 3.l (e).

(ii) [***]. If during any week beginning [***] before the expected [***] Initial Joint Qualification Release and ending [***] after the [***] Initial Joint Qualification Release, the quantity of NAND Flash Memory

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Wafers utilizing the [***] Process Technology Node that is started, that if completed after [***] Initial Joint Qualification Release would be designated as [***] Qualified Probed Wafers, is less than [***], Micron will reallocate the actual NAND Flash Memory Wafer starts utilizing the [***] Process Technology Node to target [***] for [***]. The foregoing measures shall be in addition to those measures that may be required of Micron under Section 3.l (e).

(iii) During any period in which Micron fails to satisfy its Qualified Probed Wafer Commitment, Intel’s Qualified Probed Wafer Commitment shall not exceed [***] of the total [***] during such period. Any such adjustment to Intel’s Qualified Probed Wafer Commitment shall not reduce Micron’s Qualified Probed Wafer Commitment, however, unless waived by Intel.

(i) [***]. Micron will make available to Intel for purchase no less than [***] of any [***] at the Singapore Fab that is available for [***] Pre-Qualified Probed Wafers, in excess of what is needed for [***] Pre-Qualified Probed Wafer starts at the Singapore Fab, to manufacture [***] Run at Risk Probed Wafers, not to exceed [***] Run at Risk Probed Wafers (the “[***] Base Run at Risk Probed Wafer Commitment”). Intel may purchase quantities up to the [***] Base Run at Risk Probed Wafer Commitment. If Intel desires to purchase quantities in excess of the [***] Base Run at Risk Probed Wafer Commitment, Micron may, in its sole discretion, offer to supply Intel such additional quantities (the “[***] Incremental Run at Risk Probed Wafer Commitment”). If the [***] Initial Joint Qualification Release is delayed, the Qualified Probed Wafers intended to be manufactured utilizing the [***] Process Technology Node that were previously scheduled to be shipped during the period of such delay may, at Intel’s election, be shipped as [***] Run at Risk Probed Wafers. Such quantity of [***] Run at Risk Probed Wafers is in addition to the [***] Base Run at Risk Probed Wafer Commitment and will be priced as if those [***] Run at Risk Probed Wafers were supplied under the [***] Incremental Run at Risk Probed Wafer Commitment. The Qualified Probed Wafer Commitment for the [***] period following the [***] Initial Joint Qualification Release will be reduced for each [***] Run at Risk Probed Wafer purchased by Intel.

(ii) [***]. Micron will make available to Intel for purchase no less than [***] of any [***] at the Singapore Fab that is available for [***] Pre-Qualified Probed Wafers, in excess of what is needed for [***] Pre-Qualified Probed Wafer starts at the Singapore Fab, to manufacture [***] Run at Risk Probed Wafers, not to exceed [***] Run at Risk Probed Wafers (the “[***] Base Run at Risk Probed Wafer Commitment” and, together with the [***] Base Run at Risk Probed Wafer Commitment, the “Base Run at Risk Probed Wafer Commitment”). Intel may purchase quantities of [***] Run at Risk Probed Wafers up to the [***] Base Run at Risk Probed Wafer Commitment. If Intel desires to purchase quantities of [***] Run at Risk Probed Wafers in excess of the [***] Base Run at Risk Probed Wafer Commitment, Micron may, in its sole discretion, offer to supply Intel such additional quantities (the “[***] Incremental Run at Risk Probed Wafer Commitment” and, together with the [***] Incremental Run at Risk Probed Wafer Commitment, the “Incremental Run at Risk Probed Wafer Commitment”). If the [***] Initial Joint Qualification Release is delayed, the Qualified Probed Wafers intended to be manufactured utilizing the [***] Process Technology Node that were previously scheduled to be shipped during the period of such delay may, at Intel’s election, be shipped as [***] Run at Risk Probed Wafers. Such quantity of [***] Run at Risk Probed Wafers is in addition to the [***] Base Run at Risk Probed Wafer Commitment and will be priced as if those [***] Run at Risk Probed Wafers were supplied under the [***] Incremental Run at Risk Probed Wafer Commitment. The Qualified Probed Wafer Commitment for the [***] period following the [***] Initial Joint Qualification Release will be reduced for each [***] Run at Risk Probed Wafer purchased by Intel.

2.2 Traceability and Data Retention. Micron agrees to maintain, or cause its relevant affiliates to maintain, its production data relating to the Probed Wafers supplied hereunder for a minimum of [***] ([***]) years. At Intel’s request, Micron will make available [***] as well as the [***] for Probed Wafers supplied to Intel hereunder. The Parties will exchange mutually agreed Probed Wafer manufacturing data via electronic or other means as mutually agreed by the Parties.

2.3 Control; Processes. Micron will, or will cause its relevant affiliates to, review with Intel any reasonable control and process mechanisms applicable to the manufacture of all Probed Wafers sold by Micron under this Agreement, including but not limited to such mechanisms that are utilized to meet or exceed the Specifications for the Probed Wafers. The Parties agree to work together in good faith to define mutually agreeable control and process mechanisms including the following: [***]; and [***]; provided, however, that Micron will not be required to bear any expense relating to Intel’s control and process mechanism requests that are in addition to those used by Micron or its relevant affiliates. Micron will promptly notify Intel of all Excursions, which will impact scheduled commitments to Intel.

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2.4 Additional Customer Requirements. Intel will inform Micron in writing of any auditable supplier requirements of Intel’s customers relating to the Singapore Fab. The Parties will work together in good faith to implement such requirements in a commercially reasonable manner.

2.5 [***] Restrictions. Without the prior written approval of Intel, Micron shall not implement a [***] or [***] with respect to the Qualified Probed Wafers Micron supplies to Intel pursuant to this Agreement.

2.6 Production Masks. Unless otherwise agreed with Intel, Micron or its subcontractors will be responsible to obtain, maintain, repair and replace masks used in the production of Probed Wafers at the Singapore Fab.

ARTICLE 3

FORECASTING; TAKE OR PAY

3.1 Forecasting for Probed Wafers.

(a) Demand Forecasts.

(i) [***] Pre-Qualified Probed Wafer Demand Forecast. On a Fiscal Monthly basis beginning on the [***] Design ID Ready Date, Intel will provide Micron with a written Demand Forecast, by Design ID, of its desired [***] Pre-Qualified Probed Wafer starts (the “[***] Pre-Qualified Probed Wafer Demand Forecast”) in quantities sufficient to satisfy the [***] Pre-Qualified Probed Wafer Commitment.

(ii) [***] Pre-Qualified Probed Wafer Demand Forecast. On a Fiscal Monthly basis beginning on the [***] Design ID Ready Date, Intel will provide Micron with a written Demand Forecast, by Design ID, of its desired [***] Pre-Qualified Probed Wafer starts (the “[***] Pre-Qualified Probed Wafer Demand Forecast”) in quantities sufficient to satisfy the [***] Pre-Qualified Probed Wafer Commitment.

(iii) [***] Run at Risk Wafer Demand Forecast. On a Fiscal Monthly basis beginning on a date no less than [***] the date that the [***] that [***] Initial Joint Qualification Release [***], Intel will provide Micron with a written Demand Forecast, by Design ID, of its [***] Run at Risk Probed Wafer needs, if any (the “[***] Run at Risk Probed Wafer Demand Forecast”).

(iv) [***] Run at Risk Wafer Demand Forecast. On a Fiscal Monthly basis beginning on a date no less than [***] the date that the [***] that the [***] Initial Joint Qualification Release [***], Intel will provide Micron with a written Demand Forecast, by Design ID, of its [***] Run at Risk Probed Wafer needs, if any (the “[***] Run at Risk Probed Wafer Demand Forecast”).

(v) Qualified Probed Wafer Demand Forecast. On a Fiscal Monthly basis beginning on a date no less than [***] the anticipated Start Date, Intel will provide Micron, either directly or via IMFT pursuant to the IMFT Services Agreement, with a written Demand Forecast of Qualified Probed Wafers it anticipates purchasing under this Agreement during the then-current Fiscal Quarter plus the next [***] ([***]) Fiscal Quarters (the “Qualified Probed Wafer Demand Forecast”). The aggregate amount of Qualified Probed Wafers in each Qualified Probed Wafer Demand Forecast (and each update thereof) will be equal to at least an amount sufficient to permit Intel to satisfy the Qualified Probed Wafer Commitment for each Order Year covered in whole or in part by the applicable Qualified Probed Wafer Demand Forecast without the need to purchase more than [***] Qualified Probed Wafers [***] during such Order Year. The Qualified Probed Wafer Demand Forecast will be [***] for the [***] and [***] thereafter. Intel will update the Qualified Probed Wafer Demand Forecast on a weekly or monthly basis, as needed, utilizing the demand planning process in effect between the Parties as of the Original Effective Date or as may be revised from time to time by mutual agreement of the Parties. Intel will base the Qualified Probed Wafer Demand Forecast on Singapore Fab yield forecasts provided by Micron. The Qualified Probed Wafer Demand Forecast will include desired Qualified Probed Wafer breakout by Design ID, Process Technology Node, process revision and probe test revision. In addition, the Qualified Probed Wafer Demand Forecast will include the level of Probe Testing, marking specification and packaging requirements, requested delivery date and place of delivery for the Qualified Probed Wafers, which information will be updated by Intel on a weekly basis as necessary.

(vi) Upside Requests. The [***] Pre-Qualified Probed Wafer Demand Forecast, [***] Pre-Qualified Probed Wafer Demand Forecast, [***] Run at Risk Probed Wafer Demand Forecast, [***] Run at Risk Probed Wafer

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Demand Forecast and Qualified Probed Wafer Demand Forecast shall be collectively referred to herein as the “Demand Forecast(s)”. If the quantity requested in any Demand Forecast exceeds the [***] Pre-Qualified Probed Wafer Commitment, [***] Pre-Qualified Probed Wafer Commitment, Qualified Probed Wafer Commitment or the Base Run at Risk Probed Wafer Commitment, as applicable, Micron may accept or reject any excess quantities requested in its sole discretion.

(b) Boundary Conditions and Obligations.

(i) In its Response to Forecast, Micron may only reject:

1. a Qualified Probed Wafer Demand Forecast to the extent the Qualified Probed Wafer Demand Forecast specifies for any given [***] wafer quantities for any specific Design ID of [***] than [***] Qualified Probed Wafers or, together with all [***] Run at Risk Probed Wafers Demand Forecasts and [***] Run at Risk Probed Wafers Demand Forecasts, [***] than [***] Qualified Probed Wafers in aggregate for all Design IDs in any given [***];

2. a [***] Run at Risk Probed Wafer Demand Forecast or [***] Run at Risk Probed Wafer Demand Forecast to the extent such Demand Forecast, together with all other Qualified Probed Wafer Demand Forecasts, specifies for any [***] wafer quantities of [***] than [***] Run at Risk Probed Wafers in aggregate for all Design IDs;

3. a Demand Forecast to the extent it specifies Probed Wafers that are not based on a Design ID approved by the JDP Committee;

4. a Qualified Probed Wafer Demand Forecast to the extent that it specifies for any given [***] Qualified Probed Wafers under this Agreement than under the Amended and Restated [***] Supplemental Wafer Supply Agreement or the Amended and Restated Wafer Supply Agreement No. 3; or

5. a Demand Forecast to the extent that it would result in Intel receiving [***] than [***] of the Singapore Fab’s [***] with respect to [***] Products, after taking into account all supply arrangements to which Intel or any of its affiliates is a party in aggregate, unless otherwise previously agreed to by the Parties.

(ii) In its Response to Forecast, Micron commits to support Intel’s Demand Forecast for [***] Qualified Probed Wafers, [***] of the Singapore Fab’s [***] with respect to [***] Products, after taking into account all supply arrangements to which Intel or any of its affiliates is a party in aggregate, as long as Intel’s Demand Forecast complies with the boundary conditions above.

(c) Response to Demand Forecast. Within a commercially reasonable period of time (or within a time period mutually agreed by the Parties from time-to-time) following Micron’s actual, direct receipt of each Demand Forecast, Micron shall furnish Intel with a written response indicating what portion of the Demand Forecast that Micron will commit to supply (the “Response to Forecast”). In each Response to Forecast, but subject to Section 3.1(b), Micron will commit to supply quantities sufficient to satisfy the [***] Pre-Qualified Probed Wafer Commitment, [***] Pre-Qualified Probed Wafer Commitment, [***] Base Run at Risk Probed Wafer Commitment, [***] Base Run at Risk Probed Wafer Commitment and Qualified Probed Wafer Commitment, as applicable. If Micron furnishes Intel with a Response to Forecast that commits to supply quantities greater than the [***] Pre-Qualified Probed Wafer Commitment, [***] Pre-Qualified Probed Wafer Commitment, [***] Base Run at Risk Probed Wafer Commitment, [***] Base Run at Risk Probed Wafer Commitment or Qualified Probed Wafer Commitment, as applicable, in an Order Year, but no greater than the applicable Demand Forecast, then the [***] Pre-Qualified Probed Wafer Commitment, [***] Pre-Qualified Probed Wafer Commitment, [***] Base Run at Risk Probed Wafer Commitment, [***] Base Run at Risk Probed Wafer Commitment and Qualified Probed Wafer Commitment, as applicable, in that Order Year shall be those greater amounts indicated in the Response to Forecast.

(d) Binding Forecast Wafers.

(i) Pre-Qualified Probed Wafers. Intel will be deemed to have committed to purchase, and Micron will be deemed to have committed to start, the Pre-Qualified Probed Wafer quantities requested by Intel in the [***] Pre-Qualified Probed Wafer Demand Forecast or the [***] Pre-Qualified Probed Wafer Demand Forecast, to the extent those quantities are consistent with the applicable Pre-Qualified Probed Wafer Commitment and not rejected pursuant to Section 3.1(b).

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(ii) Run at Risk Probed Wafers. Intel will be deemed to have committed to purchase, and Micron will be deemed to have committed to supply, the Run at Risk Probed Wafer quantities requested by Intel in the [***] Run at Risk Probed Wafer Demand Forecast or the [***] Run at Risk Probed Wafer Demand Forecast, to the extent those quantities are consistent with the [***] Base Run at Risk Probed Wafer Commitment and the [***] Base Run at Risk Probed Wafer Commitment and not rejected pursuant to Section 3.1(b).

(iii) Qualified Probed Wafers. The Qualified Probed Wafers scheduled for sale to Intel under this Agreement within the first [***] of each Demand Forecast that has been accepted by Micron in the Response to Forecast are deemed to be firm commitments and shall be binding on the Parties, provided that Intel may change the Design ID mix within any Process Technology Node in a Demand Forecast, for Qualified Probed Wafers at any time until [***] prior to the scheduled loading of the wafers in question and Micron shall commit to supply the requested Design ID mix changes in a revised Response to Forecast so long as the changes comply with the terms of Section 3.1(b) and this Section 3.1(d).

(iv) Binding Forecast Wafers. The Probed Wafers that are committed to be purchased, and supplied, or in the case of [***] Pre-Qualified Probed Wafers and [***] Pre-Qualified Probed Wafers, started, under Sections 3.1(d)(i), (d)(ii) or (d)(iii) above, shall be hereinafter referred to as the “Binding Forecast Wafer(s).”

(e) Variability. Micron will make commercially reasonable efforts to limit the [***] variability of the quantity of Binding Forecast Wafers it supplies to no more than [***] percent ([***]%) of the number of Binding Forecast Wafers for such week, and Micron will promptly notify Intel in writing of any inability to deliver timely the Binding Forecast Wafers. Micron agrees to use all commercially reasonable efforts to make up any shortfall of Binding Forecast Wafers for any given Design ID within [***] of the [***].

(i) With respect to Qualified Probed Wafers only, to the extent that Micron does not make up any shortfall of [***] Binding Forecast Wafers for any given Design ID within [***] of the [***] despite using commercially reasonable efforts to do so, Micron will allocate the [***] Qualified Probed Wafers of the same Design ID available to Micron and Intel at the end of this [***] based on the relative percentage of [***] Qualified Probed Wafers of the same Design ID that were consumed by Micron versus delivered to Intel in the [***] event and the Final Price for such [***] Qualified Probed Wafers will be the same as other Qualified Probed Wafers of the [***]. For purposes of illustration only, if in the [***] event, Micron had consumed [***] of the Qualified Probed Wafers of the Design ID experiencing the shortfall and had delivered the other [***] to Intel in the [***], then Intel would receive [***] of the Qualified Probed Wafers of that same Design ID available at the end of the [***] described above.

(ii) With respect to Qualified Probed Wafers only, to the extent that Micron does not make up any shortfall of [***] Binding Forecast Wafers for any given Design ID within [***] of the [***] despite using commercially reasonable efforts to do so, Micron will deliver the shortfall amount [***] and the Final Price for such [***] Binding Forecast Wafers will be equal to [***]. Any extraordinary costs or fees incurred by Micron to hold excess inventory or make up any shortfall are at Micron’s expense.

(f) Yield. Micron will make commercially reasonable efforts to deliver Qualified Probed Wafers under this Agreement that have a functional die yield, on a [***] basis, of no less than [***] percent ([***]%) below the [***] functional die yield for the same product during the same [***] at the Singapore Fab. For clarity, Micron will supply Intel with of the same quality of Qualified Probed Wafers as sold to internal Micron divisions.

(g) [***] Cost Forecast. Beginning on a date no less than [***] to the date that the [***] that Initial Joint Qualification Release is expected, and between [***] ([***]) and [***] ([***]) days [***] the [***] of each [***], Micron will extract from its quarterly business plan, its [***] Cost forecast and [***] forecast for the [***] Process Technology Node and/or the [***] Process Technology Node, as applicable, for the next [***], and deliver that to Intel. Throughout the duration of the Term, Micron will conduct a breakdown analysis of the final [***] Cost for the most recent [***] for the [***] Process Technology Node and/or the [***] Process Technology Node, as applicable, and an estimate of such amount for the next [***], and deliver such results to Intel.

3.2 Long Range Forecast. [***], in coordination with IMFT’s [***] business plan, Intel will provide Micron with a written demand forecast of Qualified Probed Wafers it anticipates purchasing for the remaining duration of the Term (“Long Range Demand Forecast”). Micron will provide feedback within a commercially reasonable period of time (or within a time

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period mutually agreed by the Parties from time-to-time) following IMFT’s [***] business plan review. Such Long Range Demand Forecast and Micron’s feedback are provided for informational purposes only and not binding on either Party.

3.3 Take or Pay.

(a) Subject to Section 3.l(e), to the extent that Intel fails to purchase any Binding Forecast Wafers, Intel shall be obligated to pay Micron an amount equal to the sum of the Binding Forecast Wafers it fails to purchase multiplied by the applicable Final Price per Binding Forecast Wafer as set forth in Schedule 1.

(b) To the extent that Intel fails to forecast, subject to Section 3.1(b), a quantity of Qualified Probed Wafers sufficient to meet the Qualified Probed Wafer Commitment in any Order Year (the “Foregone Wafer(s)”), Intel shall be obligated to pay Micron the sum of the difference between the Qualified Probed Wafer Commitment for the Order Year less the quantity set forth in the Qualified Probed Wafer Demand Forecast for that Order Year, multiplied by the applicable Final Price per Foregone Wafer as set forth in Schedule 1.

3.4 [***] Reviews and Reports. Each [***] during the Term, Micron shall provide Intel with a [***] report and meet with Intel to discuss [***] and the most recent [***] report. The [***] report will include [***] to the [***] to the [***], and summarize any [***] in the [***], including but not limited to [***], and other indicators that may [***]. At such meetings, the Parties shall define [***] and [***]. At Intel’s expense and discretion, but in no circumstance more than [***], Intel may elect a qualified third party accountancy firm to examine actual transactions under this Agreement and compliance to its requirements for the period that includes the current and immediately preceding [***]. Prior to attestation engagement planning by the accounting firm, the Parties will mutually agree on scope of work and timing contained within the engagement letter between the accounting firm and Intel. Micron agrees to take all reasonable steps necessary to make all relevant records available to the accounting firm’s examiners conducting the review. Intel agrees to use all reasonable efforts to coordinate and minimize impact to Micron for reasonable access, during normal business hours, without interruption to the Singapore Fab operations and upon reasonable advance notice, and only after the implementation of reasonable, as determined in Micron’s sole discretion, safeguards, including execution of a confidentiality agreement and prior approval of the representatives, to the premises, property and books and records, including [***], of the Singapore Fab to the extent necessary or appropriate in the reasonable discretion of the independent accounting firm for the purposes of investigating, confirming or determining the extent or amount of any product liability, warranty, refund or similar claims and obligations which may arise with respect to Products manufactured at the Singapore Fab under this Agreement.

ARTICLE 4

PURCHASE ORDERS; INVOICING AND PAYMENT

4.1 Placement of Purchase Orders.

(a) Pre-Qualified Probed Wafers and Run at Risk Probed Wafers. Prior to the commencement of every Fiscal Month, Intel shall place a non-cancelable blanket purchase order in writing (via e-mail or facsimile transmission) for Pre-Qualified Probed Wafers to be started and/or shipped, as applicable, and Base Run at Risk Probed Wafers and Incremental Run at Risk Probed Wafers to be shipped by Micron for the upcoming period through the applicable Initial Joint Qualification Release during the Term (each such order, a “Purchase Order”), which Purchase Order shall request a quantity of Pre-Qualified Probed Wafers and Base Run at Risk Probed Wafers and Incremental Run at Risk Probed Wafers that equals the quantity set forth in the current Response to Forecast for such period.

(b) Qualified Probed Wafers. Prior to the commencement of every Fiscal Quarter, Intel shall place a non-cancelable blanket purchase order in writing (via e-mail or facsimile transmission) for Qualified Probed Wafers to be shipped by Micron for the upcoming Fiscal Quarter during the Term (each such order, a “Purchase Order”), which Purchase Order shall request a quantity of Qualified Probed Wafers that equals the quantity set forth in the current Response to Forecast for such period.

4.2 Content of Purchase Orders. Each Purchase Order shall specify the following items: (a) Purchase Order number; (b) description and part number of each different Probed Wafer; (c) forecasted quantity of Probed Wafers for each different Design ID, and in the case of Pre-Qualified Probed Wafers shipped after [***], Base Run at Risk Probed Wafers and Incremental Run at Risk Probed Wafers, and Qualified Probed Wafers, the forecasted quantity of [***]; (d) the Estimated Price

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and total Estimated Price for each different Design ID, and total Estimated Price for all Probed Wafers ordered; and (e) other terms (if any) that are mutually agreed in writing by the Parties.

4.3 Acceptance of Purchase Order. If the quantities of Probed Wafers requested in a Purchase Order is equal to the quantity set forth in the current Response to Forecast for such upcoming Fiscal Quarter, Micron shall be deemed to accept such Purchase Order. If any Purchase Order contains any errors, Micron may accept or reject such Purchase Order, or any portions thereof, in its sole discretion.

4.4 Taxes. All transfer taxes (e.g., goods and services tax, value added tax, sales tax, service tax, business tax, etc.) imposed directly on or solely as a result of the sale, transfer or delivery of Probed Wafers and the payments therefor provided herein shall be stated separately on Micron’s invoice, shall be the responsibility of and collected from Intel, and shall be remitted by Micron to the appropriate tax authority (“Recoverable Taxes”), unless Intel provides valid proof of tax exemption prior to the effective date of the transfer of the Probed Wafers or otherwise as permitted by law prior to the time Micron is required to pay such taxes to the appropriate tax authority. When property is delivered within jurisdictions in which collection and remittance of taxes by Micron is required by law, Micron shall have sole responsibility for remittance of said taxes to the appropriate tax authorities. In the event such taxes are Recoverable Taxes and Micron does not collect tax from Intel or remit such taxes to the appropriate Governmental Entity on a timely basis, and is subsequently audited by any tax authority, liability of Intel will be limited to the tax assessment for such Recoverable Taxes, with no reimbursement for penalty or interest charges or other amounts incurred in connection therewith. Notwithstanding anything herein to the contrary, taxes other than Recoverable Taxes shall not be reimbursed by Intel, and each Party is responsible for its own respective income taxes (including franchise and other taxes based on net income or a variation thereof), taxes based upon gross revenues or receipts, and taxes with respect to general overhead, including but not limited to business and occupation taxes, and such taxes shall not be Recoverable Taxes.

4.5 Invoicing, Reconciliation & Payment.

(a) Pre-Qualified Probed Wafers. With respect to Pre-Qualified Probed Wafers of a particular Design ID, MSA will invoice Intel as follows:

(i) With respect to Pre-Qualified Probed Wafers for such Design ID, MSA will invoice Intel (i) a [***] invoice at time of shipment [***] and (ii) within [***] ([***]) Business Days following the end of each Fiscal Month for the [***] for such Design ID in the Fiscal Month immediately prior to the Fiscal Month in which such invoice is to be delivered.

(ii) With respect to the first [***] Pre-Qualified Probed Wafers, MSA will invoice Intel a [***] invoice at time of shipment [***] and will not provide a [***] due to the [***] referenced in the [***] Letter Agreement. With respect to [***] Pre-Qualified Probed Wafers in excess of [***], if any, MSA will invoice Intel (i) a [***] invoice at time of shipment [***] and (ii) within [***] ([***]) Business Days following the end of each Fiscal Month for the [***] for such Design ID in the Fiscal Month immediately prior to the Fiscal Month in which such invoice is to be delivered.

(b) Base Run at Risk Probed Wafers. With respect to Base Run at Risk Probed Wafers of a particular Design ID, MSA will invoice Intel as follows:

(i) With respect to each shipment of Base Run at Risk Probed Wafers of a particular Design ID, MSA will invoice Intel the Estimated Price for such Base Run at Risk Probed Wafers.

(ii) Within [***] ([***]) days of the [***] Initial Joint Qualification Release, Micron will calculate the Final Price for the [***] Base Run at Risk Probed Wafers supplied pursuant to the [***] Base Run at Risk Probed Wafer Commitment. If the Final Price exceeds the amounts invoiced by Micron (and paid by Intel) previously for the [***] Base Run at Risk Probed Wafers supplied pursuant to the [***] Base Run at Risk Probed Wafer Commitment, then MSA will issue Intel an invoice within [***] ([***]) days for the difference between such amounts. If the Final Price is less than the amounts invoiced by Micron (and paid by Intel) previously for the [***] Base Run at Risk Probed Wafers supplied pursuant to the [***] Base Run at Risk Probed Wafer Commitment, then MSA will issue Intel a credit memorandum within [***] ([***]) days for the difference between such amounts.

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(iii) Within [***] ([***]) days of the [***] Initial Joint Qualification Release, Micron will calculate the Final Price for the [***]Base Run at Risk Probed Wafers supplied pursuant to the [***]Base Run at Risk Probed Wafer Commitment. If the Final Price exceeds the amounts invoiced by Micron (and paid by Intel) previously for the [***]Base Run at Risk Probed Wafers supplied pursuant to the [***]Base Run at Risk Probed Wafer Commitment, then MSA will issue Intel an invoice within [***] ([***]) days for the difference between such amounts. If the Final Price is less than the amounts invoiced by Micron (and paid by Intel) previously for the [***]Base Run at Risk Probed Wafers supplied pursuant to the [***]Base Run at Risk Probed Wafer Commitment, then MSA will issue Intel a credit memorandum within [***] ([***]) days for the difference between such amounts.

(c) Qualified Probed Wafers and Incremental Run at Risk Probed Wafers. With respect to Qualified Probed Wafers and Incremental Run at Risk Probed Wafers of a particular Design ID, MSA will invoice Intel as follows:

(i) With respect to each shipment of Qualified Probed Wafers and Incremental Run at Risk Probed Wafers of a particular Design ID shipped, MSA will invoice Intel the Estimated Price for such wafers.

(ii) Within [***] business days of each Fiscal Month following a Fiscal Month in which an invoice is delivered pursuant to Section 4.5(c)(i), Micron will calculate the Final Price for the Qualified Probed Wafers and Incremental Run at Risk Probed Wafers shipped in the immediately preceding Fiscal Month. If the Final Price exceeds the Estimated Price invoiced by Micron previously in the immediately preceding Fiscal Month for the same Qualified Probed Wafers and Incremental Run at Risk Probed Wafers, then Micron will issue Intel an invoice within [***] ([***]) days for the difference between such amounts. If the Final Price is less than the Estimated Price invoiced by Micron previously in the immediately preceding Fiscal Month for the same Qualified Probed Wafers and Incremental Run at Risk Probed Wafers, then Micron will issue Intel a credit memorandum within [***] ([***]) days for the difference between such amounts.

(d) Payment. All amounts owed under this Agreement shall be stated, calculated and paid in United States Dollars. Except as otherwise specified in this Agreement, Intel shall pay the invoicing entity for the amounts due, owing, and duly invoiced under this Agreement within [***] ([***]) days following delivery of an invoice therefor to such place as the invoicing entity may reasonably direct therein.

4.6 Payment to Subcontractors. Micron shall be responsible for and shall hold Intel harmless for any and all payments to its vendors or subcontractors utilized in the performance of this Agreement.

ARTICLE 5

TITLE; RISK OF LOSS AND SHIPMENT

5.1 Title and Risk of Loss. Intel shall take title to, and assume risk of loss with respect to, the Probed Wafers that are exported from the country of manufacturing using the term [***] and for Probed Wafers that are not exported from the country of manufacturing using the term [***], in each case pursuant to INCOTERMS 2010.

5.2 Packaging. All packaging of the Probed Wafers shall be in conformance with the Specifications, Intel’s reasonable instructions, and general industry standards, and shall be reasonably resistant to damage that may occur during transportation. Marking on the packages shall be made by Micron in accordance with Intel’s reasonable instructions.

5.3 Shipment. Intel shall provide shipping instructions to Micron, shall bear all shipping costs, and shall directly pay all shipping carriers. All Probed Wafers shall be prepared for shipment in a manner that: (a) follows good commercial practice; (b) is acceptable to common carriers for shipment at the lowest rate; and (c) is adequate to ensure safe arrival. If and to the extent directed by Intel, Micron will ▇▇▇▇ all containers with necessary lifting, handling, and shipping information, Purchase Order number, date of shipment, and the names of Intel and applicable customer. At Intel’s request, Micron will provide drop-shipment of Probed Wafers to Intel’s customers. Shipment may be provided by a subcontractor to Micron.

5.4 Customs Clearance. Upon Intel’s request, Micron will promptly provide Intel with a statement of origin for all Probed Wafers and with applicable customs documentation for Probed Wafers wholly or partially manufactured outside of the country of import.

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ARTICLE 6

WARRANTY; HAZARDOUS MATERIALS; DISCLAIMER

6.1 Warranty. Micron makes the following warranties regarding the Probed Wafers furnished hereunder, which warranties shall survive any delivery, inspection, acceptance, payment, or resale of the Probed Wafers:

(a) the Qualified Probed Wafers will conform to all agreed Specifications;

(b) the Qualified Probed Wafers are free from defects in materials or workmanship; and

(c) Micron has the necessary right, title, and interest to provide the Probed Wafers to Intel and the Probed Wafers will be free of liens and encumbrances affecting title, not including any warranty of non-infringement.

6.2 Warranty Claims. Within a period of time, not to exceed the lesser of the actual warranty period applicable to the end customer for the Probed Wafer at issue or [***] ([***]) months from the date of the delivery of the Probed Wafers at issue to Intel (the “Warranty Notice Period”), Intel shall notify Micron if it believes that any Probed Wafer does not meet the warranty set forth in Section 6.1. Intel shall return such Probed Wafers to Micron as directed by Micron. If a Probed Wafer is determined not to be in compliance with such warranty, then Intel shall be entitled to return such Probed Wafer and cause Micron to replace at Micron’s expense or, at Intel’s option, receive a credit or refund of any monies paid to Micron in respect of such Probed Wafer. Such credit or refund shall in no event exceed on a per-unit basis the Final Price paid for the Probed Wafer under this Agreement, and shall not include any transfer taxes paid in respect of the Probed Wafer. The basis for such refund or credit shall be the Final Price on a per-unit basis in the month in which the returned Probed Wafer was invoiced to Intel. THE FOREGOING REMEDY IS INTEL’S SOLE AND EXCLUSIVE REMEDY FOR MICRON’S FAILURE TO MEET ANY WARRANTY OF SECTION 6.1.

6.3 Hazardous Materials.

(a) If Probed Wafers provided hereunder include Hazardous Materials as determined in accordance with applicable law, Micron represents and warrants that Micron and Micron’s employees, agents, and subcontractors actually working with such materials in providing the Probed Wafers hereunder to Intel shall be trained in accordance with applicable law regarding the nature of and hazards associated with the handling, transportation, and use of such Hazardous Materials, as applicable to Micron.

(b) To the extent required by applicable law, Micron shall provide Intel with Material Safety Data Sheets (MSDS) either prior to or accompanying any delivery of Probed Wafers to Intel.

6.4 Disclaimer. EXCEPT AS OTHERWISE EXPRESSLY PROVIDED IN THIS ARTICLE 6, THE PRE-QUALIFIED PROBED WAFERS AND RUN AT RISK PROBED WAFERS ARE SOLD “AS IS” WITH ALL FAULTS AND WITHOUT WARRANTIES OF ANY KIND. FURTHERMORE, MICRON HEREBY EXPRESSLY DISCLAIMS ALL REPRESENTATIONS AND WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SUITABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE, NON-INFRINGEMENT OR OTHERWISE, WITH RESPECT TO THE PROBED WAFERS PROVIDED UNDER THIS AGREEMENT. THE WARRANTIES WILL NOT APPLY TO: (a) ANY WARRANTY CLAIM OR ISSUE, OR DEFECT TO THE EXTENT CAUSED BY TECHNICAL MATERIALS PROVIDED OR SPECIFIED BY, THROUGH OR ON BEHALF OF INTEL, INCLUDING BUT NOT LIMITED TO PRODUCT DESIGNS, TECHNOLOGY AND TEST PROGRAMS; OR (b) ANY OF THE PROBED WAFERS THAT HAVE BEEN REPAIRED OR ALTERED, EXCEPT AS AUTHORIZED BY MICRON, OR WHICH ARE SUBJECTED TO MISUSE, NEGLIGENCE, ACCIDENT OR ABUSE.

ARTICLE 7

CONFIDENTIALITY

7.1 All information provided, disclosed or obtained in the performance of any of the Parties’ activities under this Agreement shall be subject to all applicable provisions of the Confidentiality Agreement. Furthermore, the terms and conditions of this Agreement shall be considered “Confidential Information” under the Confidentiality Agreement for which each Party is considered a “Receiving Party” under such agreement. To the extent there is a conflict between this Agreement and the Confidentiality Agreement, the terms of this Agreement shall control.

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ARTICLE 8

INDEMNIFICATION

8.1 Mutual General Indemnity. Subject to Article 9, each Indemnifying Party shall indemnify, defend and hold harmless each Indemnified Party from and against any and all Indemnified Losses based on or attributable to any Third Party Claim or threatened Third Party Claim arising under this Agreement and as a result of the negligence, gross negligence or willful misconduct of the Indemnifying Party or any of its respective officers, directors, employees, agents or subcontractors. Notwithstanding the foregoing, this Section 8.1 shall not apply to any claims or losses based on or attributable to intellectual property infringement.

8.2 Indemnification; Procedures.

(a) General Procedures. Promptly after the receipt by any Indemnified Party of a notice of any Third Party Claim that an Indemnified Party seeks to be indemnified under this Agreement, such Indemnified Party shall give written notice of such Third Party Claim to the Indemnifying Party, stating in reasonable detail the nature and basis of each allegation made in the Third Party Claim and the amount of potential Indemnified Losses with respect to each allegation, to the extent known, along with copies of the relevant documents received by the Indemnified Party evidencing the Third Party Claim and the basis for indemnification sought . Failure of the Indemnified Party to give such notice shall not relieve the Indemnifying Party from liability on account of this indemnification, except if and only to the extent that the Indemnifying Party is actually prejudiced by such failure or delay. Thereafter, the Indemnified Party shall deliver to the Indemnifying Party, promptly after the Indemnified Party’s receipt thereof, copies of all notices and documents (including court papers) received by the Indemnified Party relating to the Third Party Claim. The Indemnifying Party shall have the right to assume the defense of the Indemnified Party with respect to such Third Party Claim upon written notice to the Indemnified Party delivered within thirty (30) days after receipt of the particular notice from the Indemnified Party. So long as the Indemnifying Party has assumed the defense of the Third Party Claim in accordance herewith and notified the Indemnified Party in writing thereof, (i) the Indemnified Party may retain separate co-counsel at its sole cost and expense and participate in the defense of the Third Party Claim, it being understood that the Indemnifying Party shall pay all reasonable costs and expenses of counsel for the Indemnified Party after such time as the Indemnified Party has notified the Indemnifying Party of such Third Party Claim and prior to such time as the Indemnifying Party has notified the Indemnified Party that it has assumed the defense of such Third Party Claim; (ii) the Indemnified Party shall not file any papers or, other than in connection with a settlement of the Third Party Claim, consent to the entry of any judgment without the prior written consent of the Indemnifying Party (not to be unreasonably withheld, conditioned or delayed); and (iii) the Indemnifying Party will not consent to the entry of any judgment or enter into any settlement with respect to the Third Party Claim (other than a judgment or settlement that is solely for money damages and is accompanied by a release of all indemnifiable claims against the Indemnified Party) without the prior written consent of the Indemnified Party (not to be unreasonably withheld, conditioned or delayed). Whether or not the Indemnifying Party shall have assumed the defense of the Indemnified Party for a Third Party Claim, such Indemnifying Party shall not be obligated to indemnify and hold harmless the Indemnified Party hereunder for any consent to the entry of judgment or settlement entered into with respect to such Third Party Claim without the Indemnifying Party’s prior written consent, which consent shall not be unreasonably withheld, conditioned or delayed.

(b) Equitable Remedies. In the case of any Third Party Claim where the Indemnifying Party reasonably believes that it would be appropriate to settle such Third Party Claim using equitable remedies, the Indemnifying Party and the Indemnified Party shall work together in good faith to agree to a settlement; provided, however, that no Party shall be under any obligation to agree to any such settlement.

(c) Treatment of Indemnification Payments; Insurance Recoveries. Any indemnity payment under this Agreement shall be decreased by any amounts actually recovered by the Indemnified Party under third party insurance policies with respect to such Indemnified Losses (net of any premiums paid by such Indemnified Party under the relevant insurance policy), each Party agreeing (i) to use all reasonable efforts to recover all available insurance proceeds and (ii) to the extent that any indemnity payment under this Agreement has been paid by the Indemnifying Party to the Indemnified Party prior to the recovery by the Indemnified Party of such insurance proceeds, the amount of such insurance proceeds actually recovered by the Indemnified Party shall be promptly paid to the Indemnifying Party.

(d) Certain Additional Procedures. The Indemnified Party shall cooperate and assist the Indemnifying Party in determining the validity of any Third Party Claim for indemnity by the Indemnified Party and in otherwise resolving

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such matters. The Indemnified Party shall cooperate in the defense by the Indemnifying Party of each Third Party Claim (and the Indemnified Party and the Indemnifying Party agree with respect to all such Third Party Claim that a common interest privilege agreement exists between them), including: (i) permitting the Indemnifying Party to discuss the Third Party Claim with such officers, employees, consultants and representatives of the Indemnified Party as the Indemnifying Party reasonably requests; (ii) providing to the Indemnifying Party copies of documents and samples of products as the Indemnifying Party reasonably requests in connection with defending such Third Party Claim; (iii) preserving all properties, books, records, papers, documents, plans, drawings, electronic mail and databases relating to pertinent matters under the Indemnified Party’s custody or control in accordance with such Party’s corporate documents retention policies, or longer to the extent reasonably requested by the Indemnifying Party; (iv) notifying the Indemnifying Party promptly of receipt by the Indemnified Party of any subpoena or other third party request for documents or interviews and testimony; (v) providing to the Indemnifying Party copies of any documents produced by the Indemnified Party in response to or compliance with any subpoena or other third party request for documents; and (vi) except to the extent inconsistent with the Indemnified Party’s obligations under applicable law and except to the extent that to do so would subject the Indemnified Party or its employees, agents or representatives to criminal or civil sanctions, unless ordered by a court to do otherwise, not producing documents to a third party until the Indemnifying Party has been provided a reasonable opportunity to review, copy and assert privileges covering such documents.

ARTICLE 9

LIMITATION OF LIABILITY

9.1 Damages Limitation. SUBJECT TO SECTION 9.4, IN NO EVENT SHALL EITHER PARTY BE LIABLE TO THE OTHER PARTY FOR ANY SPECIAL, CONSEQUENTIAL, INCIDENTAL OR OTHER INDIRECT DAMAGES OR ANY PUNITIVE OR EXEMPLARY DAMAGES ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, WHETHER SUCH DAMAGES ARE BASED ON BREACH OF CONTRACT, TORT (INCLUDING NEGLIGENCE) OR OTHER THEORY OF LIABILITY, AND EVEN IF A PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

9.2 Remedy. THE PARTIES AGREE THAT TO THE EXTENT A CLAIM ARISES UNDER THIS AGREEMENT, THE CLAIM SHALL BE BROUGHT UNDER THIS AGREEMENT.

9.3 Damages Cap. SUBJECT TO SECTION 9.4, IF EITHER PARTY SHALL BE LIABLE TO THE OTHER PARTY FOR ANY MATTER ARISING FROM THIS AGREEMENT, WHETHER BASED UPON AN ACTION OR CLAIM IN CONTRACT, WARRANTY, EQUITY, NEGLIGENCE, INTENDED CONDUCT OR OTHERWISE (INCLUDING ANY ACTION OR CLAIM ARISING FROM AN ACT OR OMISSION, NEGLIGENT OR OTHERWISE, OF THE LIABLE PARTY), THE AMOUNT OF DAMAGES RECOVERABLE AGAINST THE LIABLE PARTY WITH RESPECT TO ANY BREACH, PERFORMANCE, NONPERFORMANCE, ACT OR OMISSION HEREUNDER WILL NOT EXCEED THE LESSER OF THE ACTUAL DAMAGES ALLOWED HEREUNDER OR TEN MILLION DOLLARS ($10,000,000).

9.4 Exclusions and Mitigation. Section 9.1 and 9.3 will not apply to either Party’s breach of Article 7. Section 9.3 will not apply to Intel’s failure to meet a payment obligation which is due and payable under this Agreement. Each Party shall have a duty to use commercially reasonable efforts to mitigate damages for which the other Party is responsible.

9.5 Losses. Except as provided under Section 8.1, Micron and Intel each shall be responsible for Losses to their respective tangible personal or real property (whether owned or leased), and each Party agrees to look only to their own insurance arrangements with respect to such damages. Micron and Intel waive all rights to recover against each other, including each Party’s insurers’ subrogation rights, if any, for any loss or damage to their respective tangible personal property or real property (whether owned or leased) from any cause covered by insurance maintained by each of them, including their respective deductibles or self-insured retentions. Notwithstanding the foregoing, in the event of a loss hereunder involving a property, transit or crime event or occurrence that: (a) is insured under Intel’s insurance policies; (b) a single insurance deductible applies; and (c) the loss event or occurrence affects the insured ownership or insured legal interests of the Parties, then the Parties shall share the cost of the deductible in proportion to each Party’s insured ownership or legal interests in relative proportion to the total insured ownership or legal interests of the Parties.

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ARTICLE 10

TERM AND TERMINATION

10.1 Term. The term of this Agreement commences on January 31, 2014 and continues in effect until the third (3rd) anniversary of the Start Date, unless terminated sooner pursuant to Section 10.2 (such period of time, the “Term”).

10.2 Termination. This Agreement may be terminated by Intel by written notice to Micron upon a material breach of this Agreement by Micron or by Micron by written notice to Intel upon a material breach of this Agreement by Intel, in each case if such breach remains uncured ninety (90) days following notice by the nonbreaching Party; provided, however, that such cure period shall be thirty (30) days if the material breach is a failure to pay monies due under this Agreement.

10.3 Survival. Termination of this Agreement shall not affect any of the Parties’ respective rights accrued or obligations owed before termination, including any rights or obligations of the Parties in respect of any accepted Purchase Orders existing at the time of termination. In addition, the following shall survive termination of this Agreement for any reason: Sections 3.3, 6.2 and 6.4, and Articles 4, 7, 8, 9, 10 and 11.

ARTICLE 11

MISCELLANEOUS

11.1 Force Majeure Events. The Parties shall be excused from any failure to perform any obligation hereunder to the extent such failure is caused by a Force Majeure Event. A Force Majeure Event shall operate to excuse a failure to perform an obligation hereunder only for the period of time during which the Force Majeure Event renders performance impossible or infeasible and only if the Party asserting Force Majeure as an excuse for its failure to perform has provided written notice to the other Party specifying the obligation to be excused and describing the events or conditions constituting the Force Majeure Event. As used herein, “Force Majeure Event” means the occurrence of an event or circumstance beyond the reasonable control of the party failing to perform, including (a) explosions, fires, flood, earthquakes, catastrophic weather conditions, or other elements of nature or acts of God; (b) acts of war (declared or undeclared), acts of terrorism, insurrection, riots, civil disorders, rebellion or sabotage; (c) acts of federal, state, local or foreign governmental authorities or courts; (d) labor disputes, lockouts, strikes or other industrial action, whether direct or indirect and whether lawful or unlawful; (e) failures or fluctuations in electrical power or telecommunications service or equipment; and (f) delays caused by the other Party’s nonperformance hereunder.

11.2 Specific Performance. The Parties agree that irreparable damage will result if this Agreement is not performed in accordance with its terms, and the Parties agree that any damages available at law for a breach of this Agreement would not be an adequate remedy. Therefore, the provisions hereof and the obligations of the Parties hereunder shall be enforceable in a court of equity, or other tribunal with jurisdiction, by a decree of specific performance, and appropriate preliminary or permanent injunctive relief may be applied for and granted in connection therewith. Such remedies and all other remedies provided for in this Agreement shall, however, be cumulative and not exclusive and shall be in addition to any other remedies that a Party may have under this Agreement.

11.3 Assignment. This Agreement shall be binding upon and inure to the benefit of the permitted successors and assigns of each Party hereto. Neither this Agreement nor any right or obligation hereunder may be assigned or delegated by either Party in whole or in part to any other Person, other than a wholly-owned Subsidiary of a Party, without the prior written consent of the non-assigning Parties. Any purported assignment in violation of the provisions of this Section shall be null and void and have no effect. No assignment or delegation by any Party will relieve or release the delegating Party from any of its liabilities and obligations under this Agreement.

11.4 Compliance with Laws and Regulations. Each of the Parties shall comply with, and shall use reasonable efforts to require that its respective subcontractors comply with, Applicable Laws relating to this Agreement and the performance of a Party’s rights hereunder.

11.5 Notice. All notices and other communications hereunder shall be in writing and shall be deemed given upon (a) transmitter’s confirmation of a receipt of a facsimile transmission; (b) confirmed delivery by a standard overnight carrier or when delivered by hand; (c) the expiration of five (5) Business Days after the day when mailed in the United States by certified or registered mail, postage prepaid; or (d) delivery in Person, addressed at the following addresses (or at such other address for a party as shall be specified by like notice):

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In the case of Micron:

Micron Technology, Inc.

▇▇▇▇ ▇. ▇▇▇▇▇▇▇ ▇▇▇ ▇▇▇▇▇, ▇▇▇▇▇ ▇▇▇▇▇

Attention: General Counsel

Facsimile Number: (▇▇▇) ▇▇▇-▇▇▇▇

In the case of Intel:

Intel Corporation

▇▇▇▇ ▇▇▇▇▇▇▇ ▇▇▇▇▇▇▇ ▇▇▇▇.

Mail-Stop SC4-203

▇▇▇▇▇ ▇▇▇▇▇, ▇▇▇▇▇▇▇▇▇▇ ▇▇▇▇▇

Attention: General Counsel

Facsimile Number: (▇▇▇) ▇▇▇-▇▇▇▇

Either Party may change its address for notices upon giving ten (10) days written notice of such change to the other Party in the manner provided above.

11.6 Waiver. The failure at any time of a Party to require performance by the other Party of any responsibility or obligation required by this Agreement shall in no way affect a Party’s right to require such performance at any time thereafter, nor shall the waiver by a Party of a breach of any provision of this Agreement by the other Party constitute a waiver of any other breach of the same or any other provision nor constitute a waiver of the responsibility or obligation itself.

11.7 Severability. Should any provision of this Agreement be deemed in contradiction with the laws of any jurisdiction in which it is to be performed or unenforceable for any reason, such provision shall be deemed null and void, but this Agreement shall remain in full force in all other respects. Should any provision of this Agreement be or become ineffective because of changes in Applicable Laws or interpretations thereof, or should this Agreement fail to include a provision that is required as a matter of law, the validity of the other provisions of this Agreement shall not be affected thereby. If such circumstances arise, the Parties hereto shall negotiate in good faith appropriate modifications to this Agreement to reflect those changes that are required by Applicable Law.

11.8 Third Party Rights. Nothing in this Agreement, whether express or implied, is intended or shall be construed to confer, directly or indirectly, upon or give to any Person, other than the Parties hereto, any legal or equitable right, remedy or claim under or in respect of this Agreement or any covenant, condition or other provision contained herein.

11.9 Amendment. This Agreement may not be modified or amended except by a written instrument executed by or on behalf of each of the Parties to this Agreement.

11.10 Entire Agreement. This Agreement and the applicable provisions of the Confidentiality Agreement, which are incorporated herein and made a part hereof, together with the Exhibits and Schedules hereto and the agreements and instruments expressly provided for herein, constitute the entire agreement of the Parties hereto with respect to the subject matter hereof and supersede all prior agreements and understandings, oral and written, between the Parties hereto with respect to the subject matter hereof.

11.11 Choice of Law. This Agreement shall be construed and enforced in accordance with and governed by the laws of the State of Delaware, without giving effect to the principles of conflict of laws thereof.

11.12 Jurisdiction; Venue. Any suit, action or proceeding seeking to enforce any provision of, or based on any matter arising out of or in connection with, this Agreement shall be brought in a state or federal court located in Delaware and each of the Parties to this Agreement hereby consents and submits to the exclusive jurisdiction of such courts (and of the appropriate appellate courts therefrom) in any such suit, action or proceeding and irrevocably waives, to the fullest extent permitted by Applicable Law, any objection which it may now or hereafter have to the laying of the venue of any such suit, action or proceeding in any such court or that any such suit, action or proceeding which is brought in any such court has been

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brought in an inconvenient forum. Process in any such suit, action or proceeding may be served on any party anywhere in the world, whether within or without the jurisdiction of any such court.

11.13 Headings. The headings of the Articles and Sections in this Agreement are provided for convenience of reference only and shall not be deemed to constitute a part hereof.

11.14 Counterparts. This Agreement may be executed in several counterparts, each of which shall be deemed an original, but all of which together shall constitute one and the same instrument.

11.15 Insurance. Without limiting or qualifying Micron’s liabilities, obligations, or indemnities otherwise assumed by Micron pursuant to this Agreement, Micron shall maintain, at no charge to Intel, with companies acceptable to Intel: Commercial General Liability insurance with limits of liability not less than [***] Dollars ($[***]) per occurrence and including liability coverage for bodily injury or property damage (a) [***] and (b) arising out of [***]. Micron’s insurance shall be primary with respect to liabilities assumed by Micron in this Agreement to the extent such liabilities are the subject of Micron’s insurance, and any applicable insurance maintained by Intel shall be excess and non-contributing. The above coverage shall name Intel as additional insured as respects Micron’s work or services provided to or on behalf of Intel.

[Signature page follows]

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IN WITNESS WHEREOF, this Agreement has been duly executed by and on behalf of the Parties hereto as of the date first set forth above.



	INTEL CORPORATION
	By:	/s/ ▇▇▇▇▇ ▇▇▇▇▇▇▇▇
	Name: Title:	▇▇▇▇▇ Krzanich Chief Executive Officer

	MICRON SEMICONDUCTOR ASIA PTE. LTD.
	By:	/s/ ▇▇▇▇▇ ▇▇▇▇▇
	Name: Title:	▇▇▇▇▇ Allan Managing Director

	MICRON TECHNOLOGY, INC.
	By:	/s/ D. ▇▇▇▇ ▇▇▇▇▇▇
	Name: Title:	D. ▇▇▇▇ ▇▇▇▇▇▇ Chief Executive Officer

THIS IS THE SIGNATURE PAGE FOR THE SECOND AMENDED AND RESTATED [***] SUPPLY AGREEMENT ENTERED INTO BY AND AMONG INTEL CORPORATION, MICRON SEMICONDUCTOR ASIA PTE. LTD. AND MICRON TECHNOLOGY, INC.

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CONFIDENTIAL

EXHIBIT A

DEFINITIONS

“[***] Base Run at Risk Probed Wafer Commitment” has the meaning set forth in Section 2.1(c).

“[***] Design ID Ready Date” means the date that the [***] that the first Design ID utilizing a [***] Process Technology Node is ready to commence manufacture at the Singapore Fab.

“[***] Incremental Run at Risk Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(c).

“[***] Initial Joint Qualification Release” means the date of the Joint Qualification Release for the first Design ID to be run on the [***] Process Technology Node in the Singapore Fab [***].

“[***] Letter Agreement” shall have the meaning set forth in the recitals to this Agreement.

“[***] Pre-Qualified Probed Wafer” means a Probed Wafer with a unique Design ID utilizing a [***] Process Technology Node that is requested to be manufactured by JDP Committee at the Singapore Fab.

“[***] Pre-Qualified Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(a)(i).

“[***] Pre-Qualified Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(i).

“[***] Run at Risk Probed Wafer” means a Probed Wafer to be manufactured utilizing the [***] Process Technology Node that is requested to be started by Intel (but not requested to be started by the JDP Committee), and is started at the Singapore Fab before the [***] Initial Joint Qualification Release.

“[***] Run at Risk Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(iii).

“[***] Base Run at Risk Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(c).

“[***] Design ID Ready Date” means the date that the [***] that the first Design ID with respect to [***] Process Technology Node is ready to commence manufacture at the Singapore Fab.

“[***] Incremental Run at Risk Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(c).

“[***] Initial Joint Qualification Release” means the date of the Joint Qualification Release for the first Design ID to be run on the [***] Process Technology Node in the Singapore Fab.

“[***] Letter Agreement” shall have the meaning set forth in the recitals to this Agreement.

“[***] Pre-Qualified Probed Wafer” means a Probed Wafer with a unique Design ID utilizing a [***] Process Technology Node that is requested to be manufactured by the JDP Committee at the Singapore Fab.

“[***] Pre-Qualified Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(a)(ii).

“[***] Pre-Qualified Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(ii).

“[***] Products” means Pre-Qualified Probed Wafers, Run at Risk Probed Wafers or Qualified Probed Wafers manufactured on the [***] Process Technology Node.

“[***] Run at Risk Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(iv).

Exhibit A-1

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CONFIDENTIAL

“Accounting Ship Release” means the Fiscal Month in which Micron changes the classification of product costs associated with a respective Design ID. Such determination is evaluated on a Fiscal Monthly basis as part of Micron’s accounting policy to determine whether product costs are classified as pre-qualification research and development, or costs of goods sold. This evaluation is based on Micron’s business unit assessment of the reliability and performance of the product compared to the JDP shipment release specifications. The specific date may be earlier than the JDP shipment release date.

“Agreement” shall have the meaning set forth in the preamble to this Agreement.

“Amended and Restated [***] Supplemental Wafer Supply Agreement” means the Amended and Restated [***] Supplemental Wafer Supply Agreement, entered into as of February 10, 2017, by and among Intel, MSA and MTI.

“Amended and Restated Wafer Supply Agreement No. 3” means the Amended and Restated Wafer Supply Agreement No. 3, entered into as of February 10, 2017, by and among Intel, MSA and MTI.

“Applicable Law” means any applicable laws, statutes, rules, regulations, ordinances, orders, codes, arbitration awards, judgments, decrees or other legal requirements of any Governmental Entity.

“Base Run at Risk Probed Wafers” means either a [***] Run at Risk Probed Wafer or a [***] Run at Risk Probed Wafer, that does not exceed the applicable [***] Base Run at Risk Probed Wafer Commitment or [***] Base Run at Risk Probed Wafer Commitment, as applicable.

“Base Run at Risk Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(c).

“Binding Forecast Wafers” shall have the meaning set forth in Section 3.l (d).

“Business Day” means a day that is not a Saturday, Sunday or other day on which commercial banking institutions in the State of New York are authorized or required by Applicable Law to be closed.

“[***]” means a [***] that affects [***], including [***].

“[***]” means a [***] that [***], or [***].

“Confidentiality Agreement” means that certain Second Amended and Restated Mutual Confidentiality Agreement by and among Intel, Intel Technology Asia Pte Ltd, MTI, MSA, IMFT and IMFS, dated as of April 6, 2012, as amended.

“Demand Forecast” shall have the meaning set forth in Section 3.l (a)(vi).

“Design ID” means a design ID approved by the JDP Committee for manufacture on the [***] Process Technology Node or the [***] Process Technology Node.

“Estimated Price” is equal to Micron’s estimate of the Final Price with respect to the applicable Probed Wafer.

“Excursion” means an occurrence during production that is outside normal historical behavior as established by the Parties in writing in the applicable Specifications which may impact performance, quality, reliability or delivery commitments hereunder for Qualified Probed Wafers.

“Final Price” means the consideration to be paid by Intel to Micron for Pre-Qualified Probed Wafers, Run at Risk Probed Wafers, Qualified Probed Wafers and Foregone Wafers as calculated pursuant to Schedule 1.

“First Amended and Restated [***] Supply Agreement” shall have the meaning set forth in the preamble to this Agreement.

“Fiscal Month” means any of the twelve financial accounting months within Micron’s Fiscal Year.

“Fiscal Quarter” means any of the four financial accounting quarters within Micron’s Fiscal Year.

Exhibit A-2

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CONFIDENTIAL

“Fiscal Year” means the fiscal year of Micron for financial accounting purposes.

“Flash Memory Integrated Circuit” means a non-volatile memory integrated circuit that contains memory cells that are electrically programmable and electrically erasable whereby the memory cells consist of one or more transistors that have a floating gate, charge-trapping regions or any other functionally equivalent structure utilizing one or more different charge levels (including binary or multi-level cell structures) with or without any on-chip control, 1/0 and other support circuitry.

“Force Majeure Event” shall have the meaning set forth in Section 11.1.

“Foregone Wafers” shall have the meaning set forth in Section 3.3(b).

“GAAP” means United States generally accepted accounting principles as in effect from time to time.

“[***]” means the [***] on a [***] and are determined to be [***] which at a [***] are shown by the [***] to meet the [***] with some [***] and [***], and to have an [***].

“Governmental Entity” means any governmental authority or entity, including any agency, board, bureau, commission, court, municipality, department, subdivision or instrumentality thereof, or any arbitrator or arbitration panel.

“Hazardous Materials” means dangerous goods, chemicals, contaminants, substances, pollutants or any other materials that are defined as hazardous by relevant local, state, national, or international law, regulations and standards.

“IMFT” means IM Flash Technologies, LLC, a Delaware limited liability company.

“IMFT Services Agreement” means that certain Services Agreement by and among IMFT, Intel and MTI, dated as of September 18, 2009, as amended, including by that certain First Amendment to Services Agreement (IMFT Services to Intel) by and among IMFT, Intel and MTI, dated as of April 6, 2012.

“Incremental Run at Risk Probed Wafers” means either a [***] Run at Risk Probed Wafer in excess of the [***] Base Run at Risk Probed Wafer Commitment or a [***] Run at Risk Probed Wafer in excess of the [***] Base Run at Risk Probed Wafer Commitment, as applicable.

“Incremental Run at Risk Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(c).

“Indemnified Losses” means all direct, out-of-pocket liabilities, damages, losses, costs and expenses of any nature incurred by an Indemnified Party, including reasonable attorneys’ fees and consultants’ fees, and all damages, fines, penalties and judgments awarded or entered against an Indemnified Party, but specifically excluding any special, consequential or other types of indirect damages.

“Indemnified Party” means any of the following to the extent entitled to seek indemnification under this Agreement: Intel, Micron, and their respective affiliates, officers, directors, employees, agents, assigns and successors.

“Indemnifying Party” means the Party owing a duty of indemnification to an Indemnified Party with respect to a particular Third Party Claim.

“Initial Joint Qualification Release” means the [***] Initial Joint Qualification Release or the [***] Initial Joint Qualification Release, as applicable.

“Intel” shall have the meaning set forth in the preamble to this Agreement.

“JDP Committee” means the JDP Committee as defined in that certain Amended and Restated Joint Development Program Agreement, between MTI and Intel, dated as of April 6, 2012, as amended.

“Joint Qualification Release” means, (a) with respect to Probed Wafers utilizing a [***] Process Technology Node, the date that a unique Design ID is deemed by the JDP Committee to meet the specifications delineated in the [***] set forth in

Exhibit A-3

[***] DENOTES CONFIDENTIAL MATERIALS OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE COMMISSION PURSUANT TO A REQUEST FOR CONFIDENTIAL TREATMENT

CONFIDENTIAL

the [***] for that Design ID and (b) with respect to Probed Wafers utilizing a [***] Process Technology Node, the date that a unique Design ID is deemed by the JDP Committee to meet the specifications with respect to that particular Design ID.

“Long Range Demand Forecast” shall have the meaning set forth in Section 3.2.

“Losses” means, collectively, any and all insurable liabilities, damages, losses, costs and expenses (including reasonable attorneys’ and consultants’ fees and expenses).

“[***] Binding Forecast Wafers” means a Binding Forecast Wafers having a [***].

“[***]” means an [***] percent ([***]%), [***]. For purposes of this Agreement, once a Design ID has [***] such Design ID will be treated as [***] during the remainder of this Agreement.

“Micron” shall have the meaning set forth in the preamble to this Agreement.

“MSA” shall have the meaning set forth in the preamble to this Agreement.

“MTI” shall have the meaning set forth in the preamble to this Agreement.

“NAND Flash Memory Integrated Circuit” means a Flash Memory Integrated Circuit in which the memory cells included in the Flash Memory Integrated Circuit are arranged in groups of serially connected memory cells (each such group of serially connected memory cells called a “string”) in which the drain of each memory cell of a string (other than the first memory cell in the string) is connected in series to the source of another memory cell in such string, the gate of each memory cell in such string is directly accessible, and the drain of the uppermost bit of such string is coupled to the bitline of the memory array.

“NAND Flash Memory Wafer” means a raw wafer that has been processed to the point of containing NAND Flash Memory Integrated Circuits organized in multiple semiconductor die and that has undergone Probe Testing, but before singulation of said die into individual semiconductor die.

“[***] Binding Forecast Wafers” means Binding Forecast Wafers [***].

“[***] Qualified Probed Wafers” means Qualified Probed Wafers [***].

“Order Year” shall have the meaning set forth in Section 2.1(b).

“Original Agreement” shall have the meaning set forth in the preamble to this Agreement.

“Original Effective Date” shall have the meaning set forth in the preamble to this Agreement.

“Party” and “Parties” shall have the meaning set forth in the preamble to this Agreement.

“Person” means any natural person and any corporation, firm, partnership, trust, estate, limited liability company, or other entity resulting from any form of association.

“Pre-Qualified Probed Wafer” means either a [***] Pre-Qualified Probed Wafer or a [***] Pre-Qualified Probed Wafer, as applicable.

“Pre-Qualified Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(a)(ii).

“Prime Wafer” means the raw silicon wafers required, on a product-by-product basis, to manufacture Probed Wafers.

“Probe Testing” means testing, using a wafer test program as set forth in the applicable Specifications, of a wafer that has completed all processing steps deemed necessary to complete the creation of the desired NAND Flash Memory Integrated Circuits in the die on such wafer, the purpose of which test is to determine how many and which of the die meet the applicable criteria for such die set forth in the Specifications.

Exhibit A-4

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CONFIDENTIAL

“Probed Wafer” means a Prime Wafer that, using either the [***] or [***] Process Technology Node, has been processed to the point of containing NAND Flash Memory Integrated Circuits organized in multiple semiconductor die (but before singulation of said die into individual semiconductor dice), that has undergone Probe Testing and any other mutually agreed upon special processing or handling.

“Process Technology Node” means a process with a known feature size or number of tiers or decks that is differentiated from another or others that have a different feature size or number of tiers or decks that yields at least a [***] percent ([***]%) difference in [***] relative to each other. For clarity, a difference in the number of [***] shall not be considered a different process node for purposes of this definition of “Process Technology Node.”

“Purchase Order” shall have the meaning set forth in Section 4.1(a) or Section 4.1(b), as applicable.

“Qualified Probed Wafer” means a Probed Wafer with a unique Design ID that is completed at the Singapore Fab after the applicable Initial Joint Qualification Release, but which is not a Pre-Qualified Probed Wafer or a Run at Risk Probed Wafer.

“Qualified Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(b).

“Qualified Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(v).

“Recoverable Taxes” shall have the meaning set forth in Section 4.4.

“Response to Forecast” shall have the meaning set forth in Section 3.l(c).

“Run at Risk Probed Wafer” means either a [***] Run at Risk Probed Wafer or a [***] Run at Risk Probed Wafer, as applicable.

“Singapore Fab” means the wafer fabrication plants located in Singapore that are now or hereafter owned by Micron.

“Specifications” means those specifications used to describe, characterize, and define the yield, quality and performance of the Probed Wafers, including any interim performance specifications at Probe Testing, as such specifications may be agreed from time to time by the JDP Committee.

“Start Date” means the date of the [***] Initial Joint Qualification Release.

“Subsidiary” means as to any Person, a corporation, partnership, limited liability company or other entity of which shares of stock or other ownership interests having ordinary voting power (other than stock or such other ownership interests having such power only by reason of the happening of a contingency) to elect a majority of the board of directors or other managers of such corporation, partnership or other entity are at the time owned, or the management of which is otherwise controlled, directly or indirectly through one or more intermediaries, or both, by such Person.

“Term” shall have the meaning set forth in Section 10.1.

“Third Party Claim” means any claim, demand, action, suit or proceeding, and any actual or threatened lawsuit, complaint, cross-complaint or counter-complaint, arbitration or other legal or arbitral proceeding of any nature, brought in any court, tribunal or judicial forum anywhere in the world, regardless of the manner in which such proceeding is captioned or styled, by any Person other than Intel, Micron and affiliates of the foregoing, against an Indemnified Party, in each case alleging entitlement to any Indemnified Losses pursuant to any indemnification obligation under this Agreement.

“[***] Cost” means the calculation referenced on Schedule 2.

“Warranty Notice Period” shall have the meaning set forth in Section 6.2.

“WOPW” means Probed Wafers processed and shipped to Intel per week.

Exhibit A-5

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CONFIDENTIAL

SCHEDULE 1

PRICE

“Final Price” means the following


(a)	With respect to Base Run at Risk Probed Wafers of [*], Final Price equals: (i) the total of [] Costs [] for []; (ii) plus [] the amount []; and (iii) which such [] is then [*].


(b)	With respect to Qualified Probed Wafers and Incremental Run at Risk Probed Wafers of [*], Final Price equals: (i) the total of [] Costs [] for []; (ii) plus [] the amount []; and (iii) which such [] is then [*].


(c)	With respect to Pre-Qualified Probed Wafers, Final Price equals the [***] as contemplated in Section 4.5(a).


(d)	With respect to each Foregone Wafer, Final Price equals: (i) the total [*] Costs [] in which such Foregone Wafer []; (ii) plus [] the amount []; and (iii) which such [] is then [].Foregone Wafers will be deemed to exist (and will be invoiced) [], subject to Section 3.1 (b), [**].

Schedule 1

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CONFIDENTIAL

SCHEDULE 2

COST

“[***] Cost” means all of the following to the extent attributable to Micron’s [***] of the Probed Wafers in accordance with this Agreement in a [***]. [***] Cost will [***], but will [***].

Separate from any determination of “[***] Costs”, [***] will be reported [***]. Micron will [***] in the applicable [***], such excluding any [***] within the applicable [***]. Micron will [***] under Section 4.5. For clarity, the [***].

Example:

[***]

[***] Cost will [***] to the extent that the [***] Probed Wafers [***] at the Singapore Fab [***] of the [***] such Probed Wafers.

Schedule 2

SECOND AMENDED AND RESTATED [***] SUPPLY AGREEMENT

Document Metadata

Document Metadata

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