Exhibit 10.2
PATENT PURCHASE AGREEMENT
This PATENT PURCHASE AGREEMENT ("Agreement") is entered into as of April 13,
2004 ("Effective Date") by and between Purple Mountain Server LLC with an
office at ▇▇▇ ▇▇▇▇ ▇▇. #▇▇▇, ▇▇▇ ▇▇▇▇▇, ▇▇▇▇▇▇▇▇▇▇ ▇▇▇▇▇ ("Purchaser"), and
Ramtron International Corporation and Enhanced Memory Systems, Inc., each
with an office at ▇▇▇▇ ▇▇▇▇▇▇▇ ▇▇▇▇▇, ▇▇▇▇▇▇▇▇ ▇▇▇▇▇▇▇, ▇▇▇▇▇▇▇▇ ▇▇▇▇▇
(together, "Seller"). The parties hereby agree as follows.
1. BACKGROUND
1.1 Seller has ownership rights in certain United States Letters Patents
and/or applications for United States Letters Patents and/or related
foreign patents and applications.
1.2 Seller wishes to sell its right, title and interest in such patents and
applications to Purchaser.
1.3 Purchaser wishes to purchase such patents and applications.
2. DEFINITIONS
2.1 "Assignment Agreements" means the agreements assigning ownership of the
Patents from the inventors and/or prior owners to Seller.
2.2 "List of Prosecution Counsel" means the names and addresses of
prosecution counsel who prosecuted the Patents and who are currently
handling the Patents.
2.3 "Patents" means those patents and applications listed in Exhibit A
hereto, and all reissues, reexaminations, Extensions, continuations,
continuations in part, continuing prosecution applications, and
divisions of such patents and applications; provisional patent
applications that are or will be continuations or continuations in part
of such patents and applications; and foreign counterparts to any of the
foregoing including without limitation of utility models.
3. DELIVERY AND PAYMENT
3.1 Delivery. Within ten (10) days following the Effective Date, Seller
shall deliver to Purchaser an executed copy of the Assignment of Patent
Rights in Exhibit B hereto, the Assignment Agreements, the List of
Prosecution Counsel, and all files and original documents owned or
controlled by Seller (including without limitation Letters Patents)
relating to the Patents except to the extent subject to a privilege or
duty of confidentiality owed to a third party including, without
limitation, all prosecution files for pending patent applications
included in the Patents, and its own files relating to the issued
Patents. Seller shall be entitled to retain a copy of the foregoing
documents for its files.
Page-1
3.2 Payment. Within ten (10) days following Seller's delivery to Purchaser
of the items listed in Section 3.1, Purchaser shall pay to Seller the
amount of one million five hundred thousand dollars ($1,500,000.00).
4. TRANSFER OF PATENTS
4.1 Patent Assignment. Subject to the grant-back license of Section 4.3,
Seller hereby sells, assigns, transfers and conveys to Purchaser all
right, title and interest it has in and to the Patents and all
inventions and discoveries described therein, including without
limitation, all rights of Seller under the Assignment Agreements, and
all rights of Seller to collect royalties under such patents.
4.2 Assignment of Causes of Action. Subject to the grant-back license of
Section 4.3, Seller hereby sells, assigns, transfers and conveys to
Purchaser all right, title and interest it has in and to all causes of
action and enforcement rights, whether currently pending, filed, or
otherwise, for the Patents and all inventions and discoveries described
therein, including without limitation all rights to pursue damages,
injunctive relief and other remedies for past, current and future
infringement of the Patents.
4.3 License Back. Purchaser hereby grants to Seller a non-exclusive,
royalty-free, fully paid-up, perpetual, irrevocable, worldwide right and
license to make, have made, import, use, sell, and offer for sale
products under the Patents assigned to Purchaser hereunder or any of
them. This license shall survive the termination of this Agreement for
any reason.
4.4 Limitation on Transferability. The license described in Section 4.3 is
not transferable or assignable except to a buyer of all, or
substantially all, of Seller's operating assets (other than cash), or to
a party that by merger or otherwise acquires all, or substantially all,
of Seller's outstanding capital stock (the "Buyer"). In the event of
such a transaction, this license shall automatically become limited to
the products, processes and services of Seller that are commercially
released as of the effective date of the acquisition and for subsequent
new versions that have merely incremental differences from such
products, processes and services; provided, however, that revenue
received from the license, sale or other disposition of any such
products, processes or services shall be allowed to grow, from the time
of acquisition, merger or purchase, up to an annual rate of 20%;
provided further, that in the event of revenue growth at a rate in
excess of 20% the Buyer and Purchaser shall negotiate in good faith a
reasonable royalty on such excess revenue to be paid to Purchaser, which
royalty rate shall be at least as favorable to Buyer as that of
Purchaser's other similarly-situated licensees. Notwithstanding
anything herein to the contrary, in no event shall the license
transferred as described in this Section 4.4 include any products,
processes or services of the non-Buyer party(ies) to the acquisition,
merger or purchase, which products, processes or services would not have
been subject to the license described in Section 4.3.
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5. ADDITIONAL OBLIGATIONS
5.1 Further Cooperation. At the reasonable request of Purchaser and at
Purchaser's sole expense, Seller shall execute and deliver such other
instruments and do and perform such other acts and things as may be
necessary or desirable for effecting completely the consummation of the
transactions contemplated hereby, including without limitation
execution, acknowledgment and recordation of other such papers, and
using its commercially reasonable best efforts to obtain the same from
the respective inventors, as necessary or desirable for fully perfecting
and conveying unto Purchaser the benefit of the transactions
Contemplated hereby.
5.2 Payment of Fees. Seller shall pay any maintenance fees, annuities, and
the like due on the Patents for a period of thirty (30) days following
the Effective Date.
6. REPRESENTATIONS AND WARRANTIES
Except as specifically described on Exhibit C to this Agreement , Seller
hereby represents and warrants to Purchaser as follows:
6.1 Authority. Seller has the right and authority to enter into this
Agreement and to carry out its obligations hereunder.
6.2 Title and Contest. Seller has good and marketable title to the Patents,
including without limitation all rights, title, and interest in the
Patents to ▇▇▇ for infringement thereof. The Patents are free and clear
of all liens, mortgages, security interests or other encumbrances, and
restrictions on transfer. To Seller's knowledge, there are no actions,
suits, investigations, claims or proceedings threatened, pending or in
progress relating in any way to the Patents. There are no existing
contracts, agreements, options, commitments, proposals, bids, offers, or
rights with, to, or in any person to acquire any of the Patents.
6.3 Existing Licenses. To Seller's knowledge, no rights or licenses have
been granted under the Patents.
6.4 Restrictions on Rights. Purchaser will not be subject to any covenant
not to ▇▇▇ or similar restrictions on its enforcement or enjoyment of
the Patents as a result of the transaction contemplated in this
Agreement, or any prior transaction related to the Patents.
6.5 Conduct. None of Seller or its representatives has engaged in any
conduct, or omitted to perform any necessary act, the result of which
would invalidate any of the Patents or hinder their enforcement,
including but not limited to misrepresenting Seller's patent rights to a
standard-setting organization.
Page-3
6.6 Enforcement. Seller has not put a third party on notice of actual or
potential infringement of any of the Patents or considered enforcement
action(s) with respect to any of the Patents.
6.7 Patent Office Proceedings. None of the Patents have been or are
currently involved in any reexamination, reissue, interference
proceeding, or any similar proceeding and that no such proceedings are
pending or threatened.
6.8 Fees. All maintenance fees, annuities, and the like due on the Patents
have been timely paid.
6.9 Consents. Seller has obtained all third party consents, approvals,
and/or other authorizations required to make the assignments of Section
4.
6.10 Validity and Enforceability. The Patents have never been found invalid
or unenforceable for any reason in any administrative, arbitration,
judicial or other proceeding, and Seller has not received any notice or
information of any kind from any source suggesting that the Patents may
be invalid or unenforceable.
6.11 Third Party Agreements. Purchaser hereby acknowledges that it has
reviewed the Third Party Agreements (as such term is defined in Exhibit
C), and expressly agrees that (i) its use and ownership of the Patents
shall be subject to the terms of the Third Party Agreements, and (ii)
it shall abide by the terms of the Third Party Agreements governing or
otherwise relating to its use and ownership of the Patents. Purchaser
shall indemnify, defend (with counsel selected by Seller), and hold
harmless Seller, its directors, officers, employees, agents, and
affiliates against any liability, loss, costs, or damages arising out
of any breach of this Section 6.11. This indemnification obligation
shall survive the termination of this Agreement for any reason.
6.12 Disclaimer of Warranty. EXCEPT AS EXPRESSLY SET FORTH IN THIS
AGREEMENT, SELLER DISCLAIMS ALL REPRESENTATIONS, WARRANTIES AND
COVENANTS OF ANY KIND, EXPRESS, IMPLIED OR STATUTORY, REGARDING ANY
MATTER RELATED TO THIS AGREEMENT.
7. MISCELLANEOUS
7.1 Limitation on Consequential Damages. EXCEPT FOR LIABILITY ARISING AS A
RESULT OF A BREACH OF SECTION 6.11 AND EXCEPT FOR FRAUD, NEITHER PARTY
SHALL BE LIABLE TO THE OTHER FOR LOSS OF PROFITS, OR ANY SPECIAL,
CONSEQUENTIAL OR INCIDENTAL DAMAGES, HOWEVER CAUSED, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE. THE PARTIES ACKNOWLEDGE THAT THESE
LIMITATIONS ON POTENTIAL LIABILITIES WERE AN ESSENTIAL ELEMENT IN
SETTING CONSIDERATION UNDER THIS AGREEMENT.
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7.2 Limitation of Liability. EXCEPT FOR LIABILITY ARISING AS A RESULT OF A
BREACH OF SECTION 6.11 AND EXCEPT FOR FRAUD, PURCHASER'S TOTAL LIABILITY
UNDER THIS AGREEMENT SHALL BE THE PAYMENT OF FUNDS AS REQUIRED PURSUANT
TO SECTION 3. THE PARTIES ACKNOWLEDGE THAT THESE LIMITATIONS ON
POTENTIAL LIABILITIES WERE AN ESSENTIAL ELEMENT IN SETTING CONSIDERATION
UNDER THIS AGREEMENT.
7.3 Compliance with Laws. Notwithstanding anything contained in this
Agreement to the contrary, the obligations of the parties shall be
subject to all laws, present arid future, of any government having
jurisdiction over the parties and this transaction, and to orders,
regulations, directions or requests of any such government.
7.4 Confidentiality of Terms. The parties hereto shall keep the terms; and
existence of this Agreement and the identities of the parties hereto
confidential and shall not now or hereafter divulge any of this
information to any third party except: (a) with the prior written
consent of the other party; (b) as otherwise may be required by law or
legal process, including in confidence to legal and financial advisors
in their capacity of advising a party in such matters; (c) during the
course of litigation, so long as the disclosure of such terms and
conditions are restricted in the same manner as is the confidential
information of other litigating parties; or (d) in confidence to its
legal counsel, accountants, banks and financing sources and their
advisors solely in connection with complying with financial
transactions; provided that, in (b) through (d) above, (i) the
disclosing party shall use all legitimate and legal means available to
minimize the disclosure to third parties, including without limitation
seeking a confidential treatment request or protective order whenever
appropriate or available; and (ii) the disclosing party shall provide
the other party with at least ten (10) days prior written notice of such
disclosure.
7.5 Governing Law. Any claim arising under or relating to this Agreement
shall be governed by the internal substantive laws of the State of New
York without regard to principles of conflict of laws.
7.6 Jurisdiction. Each party hereby agrees to jurisdiction and venue in the
courts of the State of California or the Federal courts sitting therein
for all disputes and litigation arising under or relating to this
Agreement.
7.7 Entire Agreement. The terms and conditions of this Agreement,
including its exhibits, constitutes the entire agreement between the
parties with respect to the subject matter hereof, and merges and
supersedes all prior and contemporaneous agreements, understandings,
negotiations and discussions. Neither of the parties shall be bound by
any conditions, definitions, warranties, understandings, or
representations with respect to the subject matter hereof other than as
expressly provided herein. The section headings contained in this
Agreement are for reference purposes only and shall not affect in any
Page-5
way the meaning or interpretation of this Agreement. No oral explanation
or oral information by either party hereto shall alter the meaning or
interpretation of this Agreement. No amendments or modifications shall
be effective unless in a writing signed by authorized representatives of
both parties. These terms and conditions will prevail notwithstanding
any different, conflicting or additional terms and conditions which may
appear on any purchase order, acknowledgment or other writing not
expressly incorporated into this Agreement. This Agreement may be
executed in two (2) or more counterparts, all of which, taken together,
shall be regarded as one and the same instrument. The following exhibits
are attached hereto and incorporated herein: Exhibit A (entitled "Patent
Rights to be, Assigned"); Exhibit B (entitled "Assignment of Patent
Rights") and Exhibit C (entitled "Exceptions to Seller's
Representations".
7.8 Notices: All notices required or permitted to be given hereunder shall
be in writing, shall make reference to this Agreement, and shall be
delivered by, hand* or dispatched by prepaid air courier or by
registered or certified airmail, postage prepaid, addressed as follows:
If to Seller If to Purchaser
Ramtron International Corporation Purple Mountain Server LLC
Enhanced Memory Systems, Inc.
▇▇▇▇ ▇▇▇▇▇▇▇ ▇▇▇▇▇ ▇▇▇ ▇▇▇▇ ▇▇. #▇▇▇
▇▇▇▇▇▇▇▇ ▇▇▇▇▇▇▇, ▇▇ ▇▇▇▇▇ ▇▇▇ ▇▇▇▇▇, ▇▇ ▇▇▇▇▇
Attn: ▇▇▇▇ ▇. ▇▇▇▇▇ Attn: Managing Director
Such notices shall be deemed served when received by addressee or, if
delivery is not accomplished by reason of some fault of the addressee,
when tendered for delivery. Either party may give written notice of a
change of address and, after notice of such change has been received,
any notice or request shall thereafter be given to such party at such
changed address.
7.9 Relationship of Parties. The parties hereto are independent
contractors. Neither party has any express or implied right or authority
to assume or create any obligations on behalf of the other or to bind
the other to any contract, agreement or undertaking with any third
party. Nothing in this Agreement shall be construed to create a
partnership, joint venture, employment or agency relationship between
Seller and Purchaser.
7.10 Equitable Relief. The parties agree that damages alone would be
insufficient to compensate the aggrieved party for a breach of this
Agreement, acknowledge that irreparable harm would result from a breach
of this Agreement, and consent to the entering of an order for
injunctive relief to prevent a breach or further breach, and the
entering of an order for specific performance to compel performance of
any obligations under this Agreement.
Page-6
7.11 Severability. The terms and conditions stated herein are declared to
be severable. If any paragraph, provision, or clause in this Agreement
shall be found or be held to be invalid or unenforceable in any
jurisdiction in which this Agreement is being performed, the remainder
of this Agreement shall be valid and enforceable and the parties shall
use good faith to negotiate a substitute, valid and enforceable
provision which most nearly effects the parties' intent in entering
into this Agreement.
7.12 Waiver. Failure by either party to enforce any term of this Agreement
shall not be deemed a waiver of future enforcement of that or any other
term in this Agreement or any other agreement that may be in place
between the parties.
7.13 Assignment. Except as described in section 4.4, the terms and
conditions of this Agreement shall inure to the benefit of the parties,
their successors, assigns and other legal representatives, and shall be
binding upon the parties, their successor, assigns and other legal
representatives.
In witness whereof, the parties have executed this Patent Purchase Agreement
as of the Effective Date:
Purple Mountain Server LLC Ramtron International Corporation
/S/ ▇▇▇▇▇ ▇▇▇▇▇▇▇ /S/ ▇▇▇▇ ▇▇▇▇▇
---------------------- -------------------
▇▇▇▇▇ ▇▇▇▇▇▇▇ ▇▇▇▇ ▇▇▇▇▇
Signature Signature
▇▇▇▇▇ ▇▇▇▇▇▇▇ ▇▇▇▇ ▇▇▇▇▇
---------------------- -------------------
Printed Name Printed Name
Authorized Person President Tech Grp
---------------------- -------------------
Title Title
20 April 2004 April 13, 2004
---------------------- -------------------
Date Date
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Enhanced Memory Systems, Inc.
/S/ ▇▇▇▇ ▇▇▇▇▇
-------------------
▇▇▇▇ ▇▇▇▇▇
Signature
▇▇▇▇ ▇▇▇▇▇
-------------------
Printed Name
Director
-------------------
Title
April 13, 2004
-------------------
Date
Page-8
Exhibit A
Patent Rights To Be Assigned
Patent or Title
Application No. Country Filing Date Assignor Inventor(s)
--------------- ------- ----------- -------- -------------------------
▇▇▇. 5,104,822 U.S. 07/30/1990 RAM Method For Creating Self-
(RAM 317) Aligned, Non-Patterned
Contact Areas And Stacked
Capacitors Using The
Method
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,162,890 U.S. 04/05/1991 RAM Stacked Capacitor With
(RAM 317 DIV) Sidewall Insulation
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 07/30/1991 RAM Method For Creating Self-
(RAM 317 JPN) Aligned, Non-Patterned
Contact Areas And Stacked
Capacitors Using The
Method
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,170,242 U.S. 05/10/1991 RAM Reaction Barrier For A
(RAM 319 CON) Multilayer Structure In
An Integrated Circuit
▇▇▇▇▇▇▇, Maekawa
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 07/13/1990 RAM Reaction Barrier For A
(RAM 319 JPN) Multilayer Structure In
An Integrated Circuit
▇▇▇▇▇▇▇, Maekawa
-----------------------------------------------------------------------------
▇▇▇. 5,075,817 U.S. 6/22/1990 RAM Trench Capacitor For
(RAM 320) Large Scale Integrated
Memory
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 06/21/1991 RAM Trench Capacitor For
(RAM 320 JPN) Large Scale Integrated
Memory
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,610,099 U.S. 06/28/1994 RAM Process For Fabricating
(RAM 321) Transistors Using
Composite Nitride
Structure
Stevens, Bailey, ▇▇▇▇▇▇
Page-9
-----------------------------------------------------------------------------
▇▇▇. 5,043,790 U.S. 04/05/1990 RAM Sealed Self Aligned
(RAM 322) Contacts Using Two
Nitrides Process
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,216,281 U.S. 08/26/1991 RAM Sealed Self Aligned
(RAM 322 CIP) Contact Incorporating A
Dopant Source
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 04/05/1991 RAM Sealed Self Aligned
(RAM 322 JPN) Contacts Using Two
Nitrides Process
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,134,310 U.S. 01/23/1991 RAM Current Supply Circuit
(RAM 324) For Driving High
Capacitance Load In An
Integrated Circuit
▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 01/23/1992 RAM Current Supply Circuit
(RAM 324 JPN) For Driving High
Capacitance Load In An
Integrated Circuit
▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,117,177 U.S. 01/23/1991 RAM Reference Generator For
(RAM 325) An Integrated Circuit
▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 01/23/1992 RAM Reference Generator For
(RAM 325 JPN) An Integrated Circuit
▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,255,222 U.S. 01/23/1991 RAM Output Control Circuit
(RAM 326) Having Continuously
Variable Drive Current
▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 01/22/1992 RAM Output Control Circuit
(RAM 326 JPN) Having Continuously
Variable Drive Current
▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,699,317 U.S. 10/06/1994 EMS Enhanced Dram With All
(RAM 343 CIP) Reads From On-Chip Cache
And All Writes To Memory
Array
Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
Page-10
-----------------------------------------------------------------------------
▇▇▇. 5,721,862 U.S. 06/02/1995 EMS Enhanced Dram With Single
(RAM 343 CON) Row SRAM Cache For All
Device Read Operations
Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 69324508.5 Germany 01/14/1993 EMS Edram With Embedded
(RAM 343 DE) Registers
Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,887,272 U.S. 07/03/1997 EMS Enhanced Dram With
(RAM 343 DIV) Embedded Registers
Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,347,357 U.S. 10/30/1998 EMS Enhanced Dram With
(RAM 343 Embedded Registers
DIV/CON) Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
App. 09/962,287 U.S. 09/24/2001 EMS Enhanced Dram With
(RAM 343 Embedded Registers
DIV/CON2) Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 01/21/1993 EMS EDRAM Having A
(RAM 343 JPN) Dynamically-Sized Cache
Memory And Associated
Method
Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,566,318 U.S. 08/02/1994 RAM Circuit With A Single
(RAM 381) Address Register That
Augments A Memory
Controller By Enabling
Cache Reads And Page-Mode
Writes
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,835,442 U.S. 03/22/1996 EMS EDRAM With Integrated
(RAM 393) Generation And Control Of
Write Enable And Column
Latch Signals And Method
For Making Same
▇▇▇▇▇▇, ▇.▇. ▇▇▇▇▇▇▇,
▇.▇. ▇▇▇▇▇▇▇
Page-11
-----------------------------------------------------------------------------
▇▇▇. 5,991,851 U.S. 05/02/1997 EMS Enhanced Signal
(RAM 417) Processing Random Access
Memory Device Utilizing A
Dram Memory Array
Integrated With An
Associated SRAM Cache And
Internal Refresh Control
Alwais, ▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,901,100 U.S. 04/01/1997 RAM First-In, First-Out
(RAM 418) Integrated Circuit Memory
Device Utilizing A
Dynamic Random Access
Memory Array For Data
Storage Implemented In
Conjunction With An
Associated Static Random
Access Memory Cache
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,072,741 U.S. 03/11/1999 RAM First-In, First-Out
(RAM 418 CIP) Integrated Circuit Memory
Device Utilizing A
Dynamic Random Access
Memory Array For Data
Storage Implemented In
Conjunction With An
Associated Static Random
Access Memory Cache
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,172,927 U.S. 03/24/2000 RAM First-In, First-Out
(RAM 418 CIP2) Integrated Circuit Memory
Device Incorporating A
Retransmit Function
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,141,281 U.S. 04/29/1998 EMS Technique For Reducing
(RAM 429) Element Disable Fuse
Pitch Requirements In An
Integrated Circuit Device
Incorporating Replaceable
Circuit Elements
▇▇▇▇▇▇, Ash
-----------------------------------------------------------------------------
▇▇▇. 6,055,192 U.S. 09/03/1998 EMS Dynamic Random Access
(RAM 430) Memory Word Line Boost
Technique Employing A
Boost-On-Writes Policy
▇▇▇▇▇▇
Page-12
-----------------------------------------------------------------------------
▇▇▇. 6,064,620 U.S. 07/08/1998 EMS Multi-Array Memory
(RAM 432) Device, And Associated
Method, Having Shared
Decoder Circuitry
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,278,646 U.S. 03/23/2000 EMS Multi-Array Memory
(RAM 432 CIP) Device And Associated
Method Having Shared
Decoder Circuitry
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,963,481 U.S. 06/30/1998 EMS Embedded Enhanced DRAM
(RAM 447) And Associated Method
Alwais, ▇▇▇▇▇▇
-----------------------------------------------------------------------------
App. 99302956.0 Europe 04/16/1999 EMS Embedded Enhanced DRAM
(RAM 447 EPO) And Associated Method
Alwais, ▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,249,840 U.S. 10/23/1998 EMS Multi-Bank Esdram With
(RAM 448) Cross-Coupled SRAM Cache
Registers
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,330,636 U.S. 01/25/1999 EMS Double Data Rate
(RAM 450) Synchronous Dynamic
Random Access Memory
Device Incorporating A
Static RAM Cache Per
Memory Bank
Bondurant, Peters, ▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,151,236 U.S. 02/29/2000 EMS Enhanced Bus Turnaround
(RAM 460) Integrated Circuit
Dynamic Random Access
Memory Device
Bondurant, Fisch,
Grieshaber, Mobley,
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,301,183 U.S. 07/27/2000 EMS Enhanced Bus Turnaround
(RAM 460 CON) Integrated Circuit
Dynamic Random Access
Memory Device
Bondurant, Fisch,
Grieshaber, Mobley,
▇▇▇▇▇▇
Page-13
-----------------------------------------------------------------------------
App. 2001-052888 Japan 02/27/2001 EMS Enhanced Bus Turnaround
(RAM 460 JPN) Integrated Circuit
Dynamic Random Access
Memory Device
Bondurant, Fisch,
Grieshaber, Mobley,
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,392,441 U.S. 06/13/2000 EMS Fast Response Circuit
(RAM 461) Moscaluk
-----------------------------------------------------------------------------
▇▇▇. 6,373,751 U.S. 05/15/2000 EMS Packet-Based Integrated
(RAM 463) Circuit Dynamic Random
Access Memory Device
Incorporating An On-Chip
Row Register Cache To
Reduce Data Access
Latencies
Bondurant
-----------------------------------------------------------------------------
▇▇▇. 6,549,472 U.S. 02/21/2002 EMS Packet-Based Integrated
(RAM 463 CON) Circuit Dynamic Random
Access Memory Device
Incorporating An On-Chip
Row Register Cache To
Reduce Data Access
Latencies
Bondurant
-----------------------------------------------------------------------------
▇▇▇. 6,646,928 U.S. 01/16/2003 EMS Packet-Based Integrated
(RAM 463 DIV) Circuit Dynamic Random
Access Memory Device
Incorporating An On-Chip
Row Register Cache To
Reduce Data Access
Latencies
▇▇▇▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,501,698 U.S. 11/01/2000 EMS Structure And Method
(RAM 464) For Hiding DRAM Cycle
Time Behind A Burst
Access
▇▇▇▇▇▇
-----------------------------------------------------------------------------
App. 09/828,283 U.S. 04/05/2001 EMS Method For Hiding A
(RAM 465) Refresh In A Pseudo-
Static Memory
▇▇▇▇▇▇
Page-14
-----------------------------------------------------------------------------
▇▇▇. 6,538,928 U.S. 10/11/2000 EMS Method For Reducing
(RAM 468) The Width Of A Global
Data Bus In A Memory
Architecture
▇▇▇▇▇▇
-----------------------------------------------------------------------------
App. 09/828,488 U.S. 04/05/2001 EMS Method And Circuit For
(RAM 487) Increasing The Memory
Access Speed Of An
Enhanced Synchronous
SDRAM
▇▇▇▇▇▇
-----------------------------------------------------------------------------
App. 10/782,386 U.S. 02/18/2004 EMS Method And Circuit For
(RAM 487 CON) Increasing The Memory
Access Speed Of An
Enhanced Synchronous
SDRAM
▇▇▇▇▇▇
-----------------------------------------------------------------------------
App. 10/178,072 U.S. 06/20/2002 RAM Method And Circuit For
(RAM 491) Increasing The Memory
Access Speed Of An
Enhanced Synchronous
SDRAM
Mobley, Peters, ▇▇▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,787,457 U.S. 10/18/1996 EMS Cached Synchronous DRAM
Architecture Allowing
Concurrent DRAM
Operations
Miller, Rogers, Tomashot,
Bondurant, Jones, Jr.,
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,289,413 U.S. 10/15/1999 EMS Cached Synchronous DRAM
Architecture Having A
Mode Register
Programmable Cache Policy
Rogers, Tomashot,
Bondurant, Jones, Jr.,
▇▇▇▇▇▇
Page-15
Exhibit B
ASSIGNMENT OF PATENT RIGHTS
For good and valuable consideration, the receipt of which is hereby
acknowledged, Ramtron International Corporation and Enhanced Memory Systems,
Inc., each having offices at ▇▇▇▇ ▇▇▇▇▇▇▇ ▇▇▇▇▇, ▇▇▇▇▇▇▇▇ ▇▇▇▇▇▇▇, ▇▇▇▇▇▇▇▇
▇▇▇▇▇ (together, "Assignor"), do hereby sell, assign, transfer and convey
unto Purple Mountain Server LLC, a Delaware limited liability company, having
an office at ▇▇▇ ▇▇▇▇ ▇▇▇▇▇▇, #▇▇▇, ▇▇▇ ▇▇▇▇▇, ▇▇▇▇▇▇▇▇▇▇ ▇▇▇▇▇ ("Assignee")
or its designees, all of Assignor's right, title and interest in and to: the
patent applications and patents listed below, any patents, registrations, or
certificates of invention issuing on any patent applications listed below,
the inventions disclosed in any of the foregoing, any and all counterpart
United States, international and foreign patents, applications and
certificates of invention based upon or covering any portion of the
foregoing, and all reissues, re-examinations, divisionals, renewals,
extensions, provisionals, continuations and continuations-in-part of any of
the foregoing (collectively "Patent Rights"):
Patent or Title
Application No. Country Filing Date Assignor Inventor(s)
--------------- ------- ----------- -------- -------------------------
▇▇▇. 5,104,822 U.S. 07/30/1990 RAM Method For Creating Self-
(RAM 317) Aligned, Non-Patterned
Contact Areas And Stacked
Capacitors Using The
Method
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,162,890 U.S. 04/05/1991 RAM Stacked Capacitor With
(RAM 317 DIV) Sidewall Insulation
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 07/30/1991 RAM Method For Creating Self-
(RAM 317 JPN) Aligned, Non-Patterned
Contact Areas And Stacked
Capacitors Using The
Method
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,170,242 U.S. 05/10/1991 RAM Reaction Barrier For A
(RAM 319 CON) Multilayer Structure In
An Integrated Circuit
▇▇▇▇▇▇▇, Maekawa
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 07/13/1990 RAM Reaction Barrier For A
(RAM 319 JPN) Multilayer Structure In
An Integrated Circuit
▇▇▇▇▇▇▇, Maekawa
Page-16
-----------------------------------------------------------------------------
▇▇▇. 5,075,817 U.S. 6/22/1990 RAM Trench Capacitor For
(RAM 320) Large Scale Integrated
Memory
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 06/21/1991 RAM Trench Capacitor For
(RAM 320 JPN) Large Scale Integrated
Memory
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,610,099 U.S. 06/28/1994 RAM Process For Fabricating
(RAM 321) Transistors Using
Composite Nitride
Structure
Stevens, Bailey, ▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,043,790 U.S. 04/05/1990 RAM Sealed Self Aligned
(RAM 322) Contacts Using Two
Nitrides Process
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,216,281 U.S. 08/26/1991 RAM Sealed Self Aligned
(RAM 322 CIP) Contact Incorporating A
Dopant Source
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 04/05/1991 RAM Sealed Self Aligned
(RAM 322 JPN) Contacts Using Two
Nitrides Process
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,134,310 U.S. 01/23/1991 RAM Current Supply Circuit
(RAM 324) For Driving High
Capacitance Load In An
Integrated Circuit
▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 01/23/1992 RAM Current Supply Circuit
(RAM 324 JPN) For Driving High
Capacitance Load In An
Integrated Circuit
▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,117,177 U.S. 01/23/1991 RAM Reference Generator For
(RAM 325) An Integrated Circuit
▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 01/23/1992 RAM Reference Generator For
(RAM 325 JPN) An Integrated Circuit
▇▇▇▇▇
Page-17
-----------------------------------------------------------------------------
▇▇▇. 5,255,222 U.S. 01/23/1991 RAM Output Control Circuit
(RAM 326) Having Continuously
Variable Drive Current
▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 01/22/1992 RAM Output Control Circuit
(RAM 326 JPN) Having Continuously
Variable Drive Current
▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,699,317 U.S. 10/06/1994 EMS Enhanced Dram With All
(RAM 343 CIP) Reads From On-Chip Cache
And All Writes To Memory
Array
Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,721,862 U.S. 06/02/1995 EMS Enhanced Dram With Single
(RAM 343 CON) Row SRAM Cache For All
Device Read Operations
Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 69324508.5 Germany 01/14/1993 EMS Edram With Embedded
(RAM 343 DE) Registers
Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,887,272 U.S. 07/03/1997 EMS Enhanced Dram With
(RAM 343 DIV) Embedded Registers
Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,347,357 U.S. 10/30/1998 EMS Enhanced Dram With
(RAM 343 Embedded Registers
DIV/CON) Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
App. 09/962,287 U.S. 09/24/2001 EMS Enhanced Dram With
(RAM 343 Embedded Registers
DIV/CON2) Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 01/21/1993 EMS EDRAM Having A
(RAM 343 JPN) Dynamically-Sized Cache
Memory And Associated
Method
Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
Page-18
-----------------------------------------------------------------------------
▇▇▇. 5,566,318 U.S. 08/02/1994 RAM Circuit With A Single
(RAM 381) Address Register That
Augments A Memory
Controller By Enabling
Cache Reads And Page-Mode
Writes
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,835,442 U.S. 03/22/1996 EMS EDRAM With Integrated
(RAM 393) Generation And Control Of
Write Enable And Column
Latch Signals And Method
For Making Same
▇▇▇▇▇▇, ▇.▇. ▇▇▇▇▇▇▇,
▇.▇. ▇▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,991,851 U.S. 05/02/1997 EMS Enhanced Signal
(RAM 417) Processing Random Access
Memory Device Utilizing A
Dram Memory Array
Integrated With An
Associated SRAM Cache And
Internal Refresh Control
Alwais, ▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,901,100 U.S. 04/01/1997 RAM First-In, First-Out
(RAM 418) Integrated Circuit Memory
Device Utilizing A
Dynamic Random Access
Memory Array For Data
Storage Implemented In
Conjunction With An
Associated Static Random
Access Memory Cache
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,072,741 U.S. 03/11/1999 RAM First-In, First-Out
(RAM 418 CIP) Integrated Circuit Memory
Device Utilizing A
Dynamic Random Access
Memory Array For Data
Storage Implemented In
Conjunction With An
Associated Static Random
Access Memory Cache
▇▇▇▇▇▇
Page-19
-----------------------------------------------------------------------------
▇▇▇. 6,172,927 U.S. 03/24/2000 RAM First-In, First-Out
(RAM 418 CIP2) Integrated Circuit Memory
Device Incorporating A
Retransmit Function
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,141,281 U.S. 04/29/1998 EMS Technique For Reducing
(RAM 429) Element Disable Fuse
Pitch Requirements In An
Integrated Circuit Device
Incorporating Replaceable
Circuit Elements
▇▇▇▇▇▇, Ash
-----------------------------------------------------------------------------
▇▇▇. 6,055,192 U.S. 09/03/1998 EMS Dynamic Random Access
(RAM 430) Memory Word Line Boost
Technique Employing A
Boost-On-Writes Policy
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,064,620 U.S. 07/08/1998 EMS Multi-Array Memory
(RAM 432) Device, And Associated
Method, Having Shared
Decoder Circuitry
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,278,646 U.S. 03/23/2000 EMS Multi-Array Memory
(RAM 432 CIP) Device And Associated
Method Having Shared
Decoder Circuitry
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,963,481 U.S. 06/30/1998 EMS Embedded Enhanced DRAM
(RAM 447) And Associated Method
Alwais, ▇▇▇▇▇▇
-----------------------------------------------------------------------------
App. 99302956.0 Europe 04/16/1999 EMS Embedded Enhanced DRAM
(RAM 447 EPO) And Associated Method
Alwais, ▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,249,840 U.S. 10/23/1998 EMS Multi-Bank Esdram With
(RAM 448) Cross-Coupled SRAM Cache
Registers
▇▇▇▇▇▇
Page-20
-----------------------------------------------------------------------------
▇▇▇. 6,330,636 U.S. 01/25/1999 EMS Double Data Rate
(RAM 450) Synchronous Dynamic
Random Access Memory
Device Incorporating A
Static RAM Cache Per
Memory Bank
Bondurant, Peters, ▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,151,236 U.S. 02/29/2000 EMS Enhanced Bus Turnaround
(RAM 460) Integrated Circuit
Dynamic Random Access
Memory Device
Bondurant, Fisch,
Grieshaber, Mobley,
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,301,183 U.S. 07/27/2000 EMS Enhanced Bus Turnaround
(RAM 460 CON) Integrated Circuit
Dynamic Random Access
Memory Device
Bondurant, Fisch,
Grieshaber, Mobley,
▇▇▇▇▇▇
-----------------------------------------------------------------------------
App. 2001-052888 Japan 02/27/2001 EMS Enhanced Bus Turnaround
(RAM 460 JPN) Integrated Circuit
Dynamic Random Access
Memory Device
Bondurant, Fisch,
Grieshaber, Mobley,
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,392,441 U.S. 06/13/2000 EMS Fast Response Circuit
(RAM 461) Moscaluk
-----------------------------------------------------------------------------
▇▇▇. 6,373,751 U.S. 05/15/2000 EMS Packet-Based Integrated
(RAM 463) Circuit Dynamic Random
Access Memory Device
Incorporating An On-Chip
Row Register Cache To
Reduce Data Access
Latencies
Bondurant
-----------------------------------------------------------------------------
▇▇▇. 6,549,472 U.S. 02/21/2002 EMS Packet-Based Integrated
(RAM 463 CON) Circuit Dynamic Random
Access Memory Device
Incorporating An On-Chip
Row Register Cache To
Reduce Data Access
Latencies
Bondurant
Page-21
-----------------------------------------------------------------------------
▇▇▇. 6,646,928 U.S. 01/16/2003 EMS Packet-Based Integrated
(RAM 463 DIV) Circuit Dynamic Random
Access Memory Device
Incorporating An On-Chip
Row Register Cache To
Reduce Data Access
Latencies
▇▇▇▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,501,698 U.S. 11/01/2000 EMS Structure And Method
(RAM 464) For Hiding DRAM Cycle
Time Behind A Burst
Access
▇▇▇▇▇▇
-----------------------------------------------------------------------------
App. 09/828,283 U.S. 04/05/2001 EMS Method For Hiding A
(RAM 465) Refresh In A Pseudo-
Static Memory
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,538,928 U.S. 10/11/2000 EMS Method For Reducing
(RAM 468) The Width Of A Global
Data Bus In A Memory
Architecture
▇▇▇▇▇▇
-----------------------------------------------------------------------------
App. 09/828,488 U.S. 04/05/2001 EMS Method And Circuit For
(RAM 487) Increasing The Memory
Access Speed Of An
Enhanced Synchronous
SDRAM
▇▇▇▇▇▇
-----------------------------------------------------------------------------
App. 10/782,386 U.S. 02/18/2004 EMS Method And Circuit For
(RAM 487 CON) Increasing The Memory
Access Speed Of An
Enhanced Synchronous
SDRAM
▇▇▇▇▇▇
-----------------------------------------------------------------------------
App. 10/178,072 U.S. 06/20/2002 RAM Method And Circuit For
(RAM 491) Increasing The Memory
Access Speed Of An
Enhanced Synchronous
SDRAM
Mobley, Peters, ▇▇▇▇▇▇▇▇
Page-22
-----------------------------------------------------------------------------
▇▇▇. 5,787,457 U.S. 10/18/1996 EMS Cached Synchronous DRAM
Architecture Allowing
Concurrent DRAM
Operations
Miller, Rogers, Tomashot,
Bondurant, Jones, Jr.,
▇▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,289,413 U.S. 10/15/1999 EMS Cached Synchronous DRAM
Architecture Having A
Mode Register
Programmable Cache Policy
Rogers, Tomashot,
Bondurant, Jones, Jr.,
▇▇▇▇▇▇
-----------------------------------------------------------------------------
Subject to the exceptions described on Exhibit C to the Patent Purchase
Agreement by and between the parties dated as of April 13, 2004, Assignor
represents, warrants and covenants that: (i) it is the sole owner, assignee
and holder of record title to the Patent Rights identified above, (ii) it has
obtained and submitted for recordation previously executed assignments for
all patent applications and patents identified above as necessary to fully
perfect its rights and title therein in accordance with governing law and
regulations in each respective jurisdiction, and (iii) it has full power and
authority to make the present assignment.
Assignor further agrees to and hereby does sell, assign, transfer and convey
unto Assignee all of its rights: (i) in and to causes of action and
enforcement rights for the Patent Rights including all rights to pursue
damages, injunctive relief and other remedies for past and future
infringement of the Patent Rights, and (ii) to apply in any or all countries
of the world for patents, certificates of invention or other governmental
grants for the Patent Rights, including without limitation under the Paris
Convention for the Protection of Industrial Property, the International
Patent Cooperation Treaty, or any other convention, treaty, agreement or
understanding. Assignor also hereby authorizes the respective patent office
or governmental agency in each jurisdiction to issue any and all patents or
certificates of invention which may be granted upon any of the Patent Rights
in the name of Assignee, as the assignee to the entire interest therein.
Assignor will, at the reasonable request of Assignee and at Assignee's sole
expense, do all things necessary, proper, or advisable, including without
limitation the execution, acknowledgment and recordation of specific
assignments, oaths, declarations and other documents on a country-by-country
basis, to assist Assignee in obtaining, perfecting, sustaining, and/or
enforcing the Patent Rights. Such assistance shall include providing, and
obtaining from the respective inventors, prompt production of pertinent facts
and documents, giving of testimony, execution of petitions, oaths, powers of
Page-23
attorney, specifications, declarations or other papers and other assistance
reasonably necessary for filing patent applications, complying with any duty
of disclosure, and conducting prosecution, reexamination, reissue,
interference or other priority proceedings, opposition proceedings,
cancellation proceedings, public use proceedings, infringement or other court
actions and the like with respect to the Patent Rights.
The terms and conditions of this Assignment shall inure to the benefit of
Assignee, its successors, assigns and other legal representatives, and shall
be binding upon Assignor, its successor, assigns and other legal
representatives.
IN WITNESS WHEREOF this Assignment of Patent Rights is executed at Ramtron
on April 13, 2004
RAMTRON INTERNATIONAL CORPORATION
/S/ ▇▇▇▇ ▇▇▇▇▇
------------------------------
By: ▇▇▇▇ ▇▇▇▇▇
Name: ▇▇▇▇ ▇▇▇▇▇
Title: President, Tech Grp.
(Signature MUST be notarized)
STATE OF COLORADO )
) ss.
COUNTY OF EL PASO )
The foregoing instrument was acknowledged before me on this 13 of April,
2004, by ▇▇▇▇ ▇▇▇▇▇ as President of Ramtron International Corporation, a
Delaware corporation.
/S/ ▇▇▇▇▇▇▇ ▇. ▇▇▇▇▇
--------------------
▇▇▇▇▇▇▇ ▇. ▇▇▇▇▇
Notary Public
My commission expires: 10-30-07
[SEAL]
Page-24
ENHANCED MEMORY SYSTEMS, INC.
/S/ ▇▇▇▇ ▇▇▇▇▇
------------------------------
By: ▇▇▇▇ ▇▇▇▇▇
Name: ▇▇▇▇ ▇▇▇▇▇
Title: Director
(Signature MUST be notarized)
STATE OF COLORADO )
) ss.
COUNTY OF EL PASO )
The foregoing instrument was acknowledged before me on this 13 of April,
2004, by ▇▇▇▇ ▇▇▇▇▇ as President of Enhanced Memory Systems, Inc., a
Delaware corporation.
/S/ ▇▇▇▇▇▇▇ ▇. ▇▇▇▇▇
--------------------
▇▇▇▇▇▇▇ ▇. ▇▇▇▇▇
Notary Public
My commission expires: 10-30-07
[SEAL]
Page-25
Exhibit C
Exceptions to Seller's Representations
The representations and warranties contained in Section 6 are hereby made
expressly subject to the disclosures below, including without limitation the
restrictions and other provisions contained in the agreements identified
below (the "Third Party Agreements").
1. "CROSS LICENSE AGREEMENT" by and between Infineon Technologies AG and
Enhanced Memory Systems Inc. dated May 7, 2002, a copy of which is
attached.
2. "Agreement for EDRAM Design and Purchase of Products" between
International Business Machines Corporation and Ramtron International
Corporation executed April 26, 1995, a copy of which is attached. The
following Patents constitute joint inventions owned by EMS and
International Business Machines Corporation.
-----------------------------------------------------------------------------
▇▇▇. 5,787,457 U.S. 10/18/1996 EMS Cached Synchronous DRAM
IBM Architecture Allowing
Concurrent DRAM
Operations
-----------------------------------------------------------------------------
▇▇▇. 6,289,413 U.S. 10/15/1999 EMS Cached Synchronous DRAM
IBM Architecture Having A
Mode Register
Programmable Cache Policy
-----------------------------------------------------------------------------
3. The following Patents are jointly owned by UMC Japan and Ramtron
International Corporation ("RIC"), previously Ramtron Corporation
("RAM"), in accordance with a Product Development and License Agreement
dated September 20, 1998, a Letter of Agreement-September 22, 1989, and a
Termination Agreement made and entered into as of May 17, 1995, copies of
which are attached. It is Ramtron's understanding that NMB Semiconductor
Company, Ltd. has undergone a number of name changes, including from NMB
Semiconductor Company, Ltd. ("NMB") to Nippon Steel Semiconductor
Corporation ("NSSC") to Nippon Foundry, Inc. ("NFI") to UMC Japan.
Registered current owners (with respect to Japanese patents) and owners
of record (with respect to U.S. patents) are listed below.
-----------------------------------------------------------------------------
▇▇▇. 5,104,822 U.S. 07/30/1990 RIC Method For Creating Self-
(RAM 317) NSSC Aligned, Non-Patterned
Contact Areas And Stacked
Capacitors Using The
Method
Page-26
-----------------------------------------------------------------------------
▇▇▇. 5,162,890 U.S. 04/05/1991 RIC Stacked Capacitor With
(RAM 317 DIV) NSSC Sidewall Insulation
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 07/30/1991 RIC Method For Creating Self-
(RAM 317 JPN) NMB Aligned, Non-Patterned
Contact Areas And Stacked
Capacitors Using The
Method
-----------------------------------------------------------------------------
▇▇▇. 5,170,242 U.S. 05/10/1991 RIC Reaction Barrier For A
(RAM 319 CON) NSSC Multilayer Structure In
An Integrated Circuit
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 07/13/1990 RAM Reaction Barrier For A
(RAM 319 JPN) NMB Multilayer Structure In
An Integrated Circuit
-----------------------------------------------------------------------------
▇▇▇. 5,075,817 U.S. 6/22/1990 RIC Trench Capacitor For
(RAM 320) NSSC Large Scale Integrated
Memory
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 06/21/1991 RIC Trench Capacitor For
(RAM 320 JPN) NMB Large Scale Integrated
Memory
-----------------------------------------------------------------------------
▇▇▇. 5,043,790 U.S. 04/05/1990 RIC Sealed Self Aligned
(RAM 322) NSSC Contacts Using Two
Nitrides Process
-----------------------------------------------------------------------------
▇▇▇. 5,216,281 U.S. 08/26/1991 RIC Sealed Self Aligned
(RAM 322 CIP) NSSC Contact Incorporating A
Dopant Source
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 04/05/1991 RIC Sealed Self Aligned
(RAM 322 JPN) NMB Contacts Using Two
Nitrides Process
-----------------------------------------------------------------------------
▇▇▇. 5,134,310 U.S. 01/23/1991 RIC Current Supply Circuit
(RAM 324) NSSC For Driving High
Capacitance Load In An
Integrated Circuit
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 01/23/1992 RIC Current Supply Circuit
(RAM 324 JPN) NFI For Driving High
Capacitance Load In An
Integrated Circuit
-----------------------------------------------------------------------------
▇▇▇. 5,117,177 U.S. 01/23/1991 RIC Reference Generator For
(RAM 325) NSSC An Integrated Circuit
Page-27
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 01/23/1992 RAM Reference Generator For
(RAM 325 JPN) NFI An Integrated Circuit
-----------------------------------------------------------------------------
▇▇▇. 5,255,222 U.S. 01/23/1991 RIC Output Control Circuit
(RAM 326) NSSC Having Continuously
Variable Drive Current
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 01/22/1992 RAM Output Control Circuit
(RAM 326 JPN) NFI Having Continuously
Variable Drive Current
-----------------------------------------------------------------------------
4. "SETTLEMENT AND LICENSE AGREEMENT" by and between Enhanced Memory
Systems, Inc. and NEC Corporation dated November 9, 1999, a copy of which
is attached. The Patents which fall within the definition of "Licensed
Patents" in this agreement are listed below.
-----------------------------------------------------------------------------
▇▇▇. 5,699,317 U.S. 10/06/1994 EMS Enhanced Dram With All
(RAM 343 CIP) Reads From On-Chip Cache
And All Writes To Memory
Array
Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,721,862 U.S. 06/02/1995 EMS Enhanced Dram With Single
(RAM 343 CON) Row SRAM Cache For All
Device Read Operations
Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 69324508.5 Germany 01/14/1993 EMS Edram With Embedded
(RAM 343 DE) Registers
Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 5,887,272 U.S. 07/03/1997 EMS Enhanced Dram With
(RAM 343 DIV) Embedded Registers
Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
▇▇▇. 6,347,357 U.S. 10/30/1998 EMS Enhanced Dram With
(RAM 343 Embedded Registers
DIV/CON) Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
App. 09/962,287 U.S. 09/24/2001 EMS Enhanced Dram With
(RAM 343 Embedded Registers
DIV/CON2) Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
Page-28
-----------------------------------------------------------------------------
▇▇▇. ▇▇▇▇▇▇▇ ▇▇▇▇▇ 01/21/1993 EMS EDRAM Having A
(RAM 343 JPN) Dynamically-Sized Cache
Memory And Associated
Method
Mobley, Sartore,
▇▇▇▇▇▇▇▇, ▇▇▇▇▇
-----------------------------------------------------------------------------
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