TLA Number LEC-TLA-00547 Legal Counsel AF Annex Effective Date 22 June 2009

Exhibit 10.7

ANNEX 1

RDA INTERNATIONAL INC.

ARM*** CORE (IP ACCESS)

TLA Number		LEC-TLA-00547
Legal Counsel		AF
Annex Effective Date		22 June 2009

This Annex, when signed by both parties, shall form part of and be incorporated into the Technology Licence Agreement (“TLA”) between the parties (document reference as identified in the table above). Solely for the purposes of interpretation of the TLA with respect to this Annex, to the extent that the provisions contained in this Annex conflict with any of the provisions of the TLA the provisions contained in this Annex shall prevail over and shall supersede the conflicting provisions in the TLA.

SECTION 1 — ARM TECHNOLOGY

Disclosure Rights

D		CONFIDENTIAL except disclosure permitted to “Designers” in accordance with Clause 3 of the TLA
M		CONFIDENTIAL except disclosure permitted to “Manufacturers” in accordance with Clause 3 of the TLA
T		CONFIDENTIAL except disclosure permitted to “Test Houses” in accordance with Clause 3 of the TLA
CS		CONFIDENTIAL except disclosure permitted to “Customers” in accordance with Clause 3 of the TLA
N		NON-CONFIDENTIAL but disclosure may be subject to license restrictions

ARM***

SECTION 1 ARM TECHNOLOGY

PART A TECHNICAL REFERENCE MANUAL

Note: TRM = Technical Reference Manual

				Disclosure
Part Number		Description		Rights		Delivery Date
AT220-DA-03001		ARM*** Core TRM PDF		N		Within ten (10) Days of Annex Effective Date
AT220-DA-00001		ARM*** Core TRM ***		D
AT230-DA-03001		ARM*** TRM PDF		N
AT230-DA-00001		ARM*** TRM ***		D
AT230-DC-11001		ARM*** Core Errata List		N
PART B IMPLEMENTATION GUIDE
				Disclosure
Part Number		Description		Rights		Delivery Date
AT230-DC-02008		ARM*** Implementation Guide		D		Within ten (10) Days of Annex Effective Date
AT230-DC-06001		ARM*** Release Information		D
PART C ARM CORE SYNTHESIZABLE SOURCE
Section 1 Synthesizable RTL
Part Number		Description		Disclosure Rights		Delivery Date
AT230-MN-22100		Synthesizable Verilog		D		Within ten (10) Day of Annex Effective Date
Section 2 Synthesis Scripts
Part Number		Description		Disclosure Rights		Delivery Date
AT230-RM-00002		Synopsys Reference Implementation Flow		D		Within ten (10) Days of Annex Effective Date
AT230-RM-00003		Magma Reference Implementation Flow		D
AT230-RM-70000		Cdn Ref. Implementation Flow (RTL to GDS)		D
AT230-DE-70003		RTL to Netlist Verplex LEC Script		D

PART D RTL TEST BENCHES

TC = Test Chip

Part Number		Description		Disclosure Rights		Delivery Date
AT231-MN-22101		Verilog Validation Environment		D		Within ten (10) Days of Annex Effective Date
PART E AVS
Part Number		Description		Disclosure Rights		Delivery Date
AT231-VA-04001		Simulation Validation Suite binaries		D		Within ten (10) Days of Annex Effective Date
PART F FUNCTIONAL TEST VECTORS
Part Number		Description		Disclosure Rights		Delivery Date
AT230-VE-70000		ARM*** Instruction Execution Vectors		D,M,T,CS		Within ten (10) Days of Annex Effective Date
AT230-VE-70002		ARM*** Speed Indicative Vectors		D,M,T,CS
AT230-VE-70004		ARM*** Power Indicative Vectors		D,M,T,CS
PART G FUNCTIONAL & INTEGRATION TEST
Part Number		Description		Disclosure Rights		Delivery Date
AT230-VE-70006		Instruction Execution Test source		D,CS		Within ten (10) Days of Annex Effective Date
AT230-VE-70007		ARM*** Speed Indicative Test Source		D,CS
AT230-VE-09001		ARM*** Power Indicative Test Source		D,CS
AT230-VE-70106		Portable Functional Test Source Code		D,CS
PART H MODELS
Part Number		Description		Disclosure Rights		Delivery Date
AT230-MS-27007		DSM - ModelSim Verilog - Linux		N		Within ten (10) Days of Annex Effective Date
AT230-MS-26007		DSM - VCS - Linux
AT230-MS-28007		DSM - NC-Verilog - Linux
AT230-MS-27010		DSM - ModelSim Verilog - Linux-AMD-64bit
AT230-MS-26010		DSM - Synopsys VCS - Linux-AMD-64bit
AT230-MS-28010		DSM - NC-Verilog - Linux-AMD-64bit

PART I

ISA is ARMv5TEJ

Memory Architecture is Harvard

Pipeline length is 5/6 stages

PART J TEST CHIP DOCUMENTATION

Part Number		Description		Disclosure Rights		Delivery Date
AT231-DA-00002		Test Chip Implementation Guide		D,M,T		Within ten (10) Days of Annex Effective Date
PART K TEST CHIP SYNTHESIZABLE SOURCE
TC = Test Chip
Section 1 Test Chip Synthesizable RTL
Part Number		Description		Disclosure Rights		Delivery Date
AT231-MN-22100		Test Chip synthesizable Verilog		D		Within ten (10) Days of Annex Effective Date
Section 2 Test Chip Synthesis Scripts
Part Number		Description		Disclosure Rights		Delivery Date
AT231-MN-01001		Test Chip Verilog synthesis command file		D		Within ten (10) Days of Annex Effective Date
PART L TEST CHIP FUNCTIONAL TEST VECTORS
Part Number		Description		Disclosure Rights		Delivery Date
AT231-VE-70000		Test Chip Instruction Execution Vectors		D,M,T,CS		Within ten (10) Days of Annex Effective Date
AT231-VE-70001		Test Chip Instruction Execution Vectors		D,M,T
AT231-VE-70004		Test Chip Power Indicative Vectors CRF		D,M,T
AT231-VE-70005		Test Chip Power Indicative Vectors WGL		D,M,T

SECTION 2 — LICENCE AND SPECIAL CONDITIONS

A.		Definitions
A.1		“Architecture” means the architecture identified in Section 1 Part I of this Annex 1.
A.2		“ARM Compliant Core” means the ARM*** microprocessor core as described and identified in the Technical Reference Manual and which;

	(i)		executes each and every instruction in the ARM Instruction Set;
	(ii)		executes no additional instructions to those contained in the ARM Instruction Set;
	(iii)		exhibits the Architecture;
	(iv)		exhibits the Pipeline Length;
	(v)		is Single Issue;
	(vi)		executes all instructions at an identical rate of cycles per instruction (“CPI”) to that specified in the Technical Reference Manual;
	(vii)		implements the programmer’s model as identified in the [“Architecture Reference Manual” (Published by ▇▇▇▇▇▇▇-▇▇▇▇▇▇);
	(viii)		runs and passes the Functional Test Vectors;
	(ix)		runs and passes the AVS; and
	(x)		has been verified in accordance with the provisions of Section 3 of this Annex 1.

A.3		“ARM Compliant Product” means an integrated circuit incorporating an ARM Compliant Core.
A.4		“ARM*** Instruction Set” means the ARM*** instruction sets as described and identified in the ARM Architecture Reference Manual ARM DDI 0100.
A.5		“ARM Instruction Set” means the instruction set identified in Section 1 Part I of this Annex 1.
A.6		“AVS” means the ARM architectural validation suite identified in Section 1 Part E of this Annex 1.
A.7		“Design Start” means the earlier of any of the following: (i) the date that LICENSEE first synthesises the Synthesisable RTL for an ARM compliant Product; (ii) the date that LICENSEE enters into a contract with a third party for the design of an ARM Compliant Product; or (iii) the date that LICENSEE delivers any ARM Technology or derivatives thereof, to a Customer pursuant to the licenses granted in this Annex 1.
A.8		“Download” means the removal or copying of any or all of the relevant ARM Technology in respect of each ARM Compliant Product from the secure area on ▇▇▇.▇▇▇▇▇▇▇.▇▇▇.▇▇▇.
A.9		“End User Licence” means a license agreement substantially in the form set out in Section 10 of this Annex 1.
A.10		“Functional and Integration Test” means the relevant test files identified in Section 1 Part G of this Annex 1.
A.11		“Functional Test Vectors” means the functional test vectors identified in Section 1 Part F of this Annex 1.

A.12		“Harvard Architecture” means a microprocessor architecture which dictates that the address and data buses for instruction fetches and for data load/store operations are separate and access separate memories for program instructions and program data.
A.13		“Implementation and Integration Documentation” means the documentation identified in Section 1 Part B of this Annex 1.
A.14		“Implementation Scripts” means the deliverables identified in Section 1 Part C Section 2 of this Annex 1.
A.15		“Models” means; (i) the design simulation models identified in Section 1 Part H; and (ii) any other design simulation model for the ARM*** microprocessor core which is generally available from ARM subject to; (a) receipt by ARM of a purchase order from LICENSEE requesting such design simulation model expressly subject to the terms and conditions of this Agreement; and (b) the payment by LICENSEE to ARM of the then current fee for such design simulation model as quoted by ARM from time to time.
A.16		“Pipeline Length” means the number of clocked stages through which each single-cycle instruction must pass to complete the execution of such instruction and identified in Section 1 Part I of this Annex 1.
A.17		“Single Issue” means that only one instruction is issued for execution within the integer unit in any single clock cycle, where for the purposes of this definition clock means the clock that advances the pipeline.
A.18		“Synthesisable RTL” means the deliverables identified in Section 1 Part C Section 1 of this Annex 1.
A.19		“Technical Reference Manual” means the relevant technical reference manuals identified in Section 1 Part A Section 1 of this Annex 1.
A.20		“Test Chip” means for each ARM Compliant Core a device which complies with the relevant Test Chip Documentation.
A.21		“Test Chip Documentation” means the relevant test chip specification identified in Section 1 Part J of this Annex 1.
A.22		“Test Chip Functional Test Vectors” means the test chip functional test vectors identified in Section 1 Part L of this Annex 1.
A.23		“Test Chip Synthesisable RTL” means the deliverables identified in Section 1 Part K Section 1 of this Annex 1.
A.24		“Test Chip Synthesis Scripts” means the deliverables identified in Section 1 Part K Section 2 of this Annex 1.
A.25		“Unique ARM Compliant Product” means:

	(i)		an unlimited number of units of a single design for an ARM Compliant Product which has been taped out and given a unique part number; and
	(ii)		an unlimited number of units of any derivatives of the ARM Compliant Products referred to in Clause A.25(i), provided that:

(a)

such derivatives result only from any or all of the following modifications; (1) the implementation by LICENSEE of an Update delivered by ARM to some or all of the ARM Technology; (2) the correction of errors in such ARM Compliant Products to achieve conformance with the original specification for such design; and (3) a version of such ARM Compliant Product that has been

ported to a different set of process design rules but is otherwise functionally unmodified (except to the extent accommodated by this definition); and

(b)

except as provided below, no more than one such derivative for the ARM Compliant Product referred to in Clause A.25(i) is being manufactured for LICENSEE at any time. LICENSEE shall be permitted to concurrently manufacture the derivative and the design from which such derivative was derived; (i) indefinitely if the derivative is a result of Clause A.25(ii)(a)(1) or Clause A.25(ii)(a)(2); and (ii) if the derivative is a result of Clause A.25(ii)(a)(3), then for a period of six (6) months from the date of first manufacture of the new derivative.

A.26		“Use” means in respect of the object code of the Models, the use of (including copying the object code of the Models to the extent that such copying is incidental to such use, including installation, backup and execution) the object code of the Models, or any part thereof. Use shall specifically exclude: (i) the translation, adaptation, arrangement or other alteration of the object code of the Models except as allowed by local legislation implementing Article 6 of the EC Directive on the legal protection of computer programs (91/250/EEC) and then only to the extent necessary to achieve interoperability of an independently created program with other programs; and (ii) the adapting or reverse compiling of the object code of the Models for the purpose of error correction.
A.27		“Validation and Verification Environment” means the program files identified in Section 1 Part D of this Annex 1.
B.		Licence
B.1		Subject to the provisions of Clause 3 (Confidentiality) of the TLA and the provisions of this Section 2, ARM hereby grants, to LICENSEE, a non-transferable (subject to Clause 16.3 of the TLA), non-exclusive, world-wide licence for the Term to;
		Technical Reference Documentation

(i)

use, copy, modify (solely to the extent necessary to reflect any permitted modifications in accordance with the provisions of this Clause B.1 or for incorporation into LICENSEE’s documentation), distribute and have distributed the Technical Reference Manuals;

ARM Compliant Core

	(ii)		use and copy the Implementation and Integration Documentation only for the purposes of designing, having designed (subject to the provisions of Clause 2.2 of the TLA) ARM Compliant Products;
	(iii)		use and copy the AVS only for the purposes of designing, having designed (subject to the provisions of Clause 2.2 of the TLA) ARM Compliant Products and Test Chips;
	(iv)		use, copy and modify the Synthesisable RTL (solely for the purposes of scan insertion, buffer insertion, timing closure, targeting standard cell libraries, direct instantiations of cells for speed and power optimisation, and use of licensee specified BIST), only for the purposes of designing, having designed (subject to the provisions of Clause 2.2 of the TLA) ARM Compliant Products;
	(v)		use, copy and modify the Implementation Scripts only for the purposes of designing, having designed (subject to the provisions of Clause 2.2 of the TLA), ARM Compliant Products;

	(vi)		use, copy and modify the Functional and Integration Test only for the purposes of designing, having designed (subject to the provisions of Clauses 2.2 and 2.3 of the TLA), ARM Compliant Products;
	(vii)		use, copy and modify (solely for the purpose of and to the extent necessary to run the vectors on a simulator or tester) the Functional Test Vectors, only for the purposes of designing and having designed (subject to the provisions of Clauses 2.2 and 2.3 of the TLA), manufacturing and having manufactured (subject to the provisions of Clause 2.4 of the TLA), testing and having tested (subject to the provisions of Clause 2.5 of the TLA) ARM Compliant Products;
	(viii)		use, copy and modify the Validation and Verification Environment only for the purposes of designing and having designed (subject to the provisions of Clause 2.2 of the TLA) ARM Compliant Products and Test Chips;
	(ix)		manufacture and have manufactured (subject to the provisions of Clause 2.4 of the TLA) the Unique ARM Compliant Products created under the licences granted in Clauses B.1(i) to B.1(viii) inclusive;
	(x)		package and have packaged (subject to the provisions of Clause 2.6 of the TLA), the Unique ARM Compliant Products manufactured under the licences granted in Clause B.1(ix);
	(xi)		sell, supply and distribute encapsulated die of the Unique ARM Compliant Products which have been manufactured under the licences granted in Clause B.1(ix);

Models

	(xii)		copy and use, internally and for third party support purposes, the Models and related documentation;
	(xiii)		use, reproduce and distribute, and sub-license (subject to the terms of an End User Licence) the Use of the object code of the Models, solely for the purpose of developing ARM Compliant Products; and
	(xiv)		modify, reproduce, use and distribute, in connection with the Models, the documentation related thereto.

Test Chips

	(xv)		use, copy and modify; (a) the Test Chip Functional Test Vectors (solely for the purposes of and to the extent necessary to run the vectors on a simulator or tester; (b) the Test Chip Synthesisable RTL (solely for the purposes of scan insertion, buffer insertion, timing closure, targeting standard cell libraries, direct instantiations of cells for speed and power optimisation, and use of licensee specified BIST and (c) the Test Chip Synthesis Scripts, only for the purposes of designing, having designed (subject to the provisions of Clause 2.2 and 2.3 of the TLA) Test Chips;
	(xvi)		use and copy the Test Chip Documentation, only for the purposes of designing and having designed (subject to the provisions of Clauses 2.2 and 2.3 of the TLA) Test Chips;
	(xvii)		manufacture and have manufactured (subject to the provisions of Clause 2.4 of the TLA) the Test Chips created under the licences granted in Clauses 2.1 (iii), (viii), (xv) and (xvi).

C.		Special Conditions
		Sun Java Hardware Acceleration
		“Sun SCSL License Agreement” means any of; (i) a Sun Community Source License entered into between LICENSEE and Sun Microsystems Inc. for the Sun CLDC technology; or (ii) any license agreement entered into between LICENSEE and Sun Microsystems Inc. which expressly permits LICENSEE to share source code for the Sun CLDC technology with ARM for the Sun CLDC technology.
		“Jazelle” means the extension to the ARM architecture that enables the execution of a subset of Java byte codes by an ARM core as accessed through the BXJ instruction.
C.1		LICENSEE acknowledges that the ARM Compliant Core incorporates hardware acceleration for Sun Microsystems Inc.’s (“Sun”) Java technology. Without prejudice to any limitations or restrictions set out in the licence grants in Clause B.1 above, LICENSEE agrees that unless LICENSEE has entered into and continues to enjoy the benefit of a Sun SCSL License Agreement, LICENSEE shall be subject to the following licensing restrictions;

	A.		LICENSEE shall not; (i) carry out or procure any functional modification of any part of the ARM*** Core to the extent that it includes, incorporates or implements Jazelle; or (ii) reverse engineer or use the ARM Technology licensed under this Annex for the purpose of implementing the whole or any part of a Java specification (where a Java specification means any “Final Release” of a “JSR” developed as part of the Java Community Process without first entering into a Sun SCSL License Agreement;
	B.		LICENSEE agrees that Sun Microsystems Inc. shall be an intended third party beneficiary of the terms and conditions of this TLA solely for the purpose of enforcing the restrictions contained in A above; and
	C.		If LICENSEE discloses or distributes any ARM Technology which includes, incorporates or implements Jazelle to a third party, except as ARM Compliant Products in the form of silicon, then such third party shall be made subject to the same restrictions as LICENSEE in A and B above.

D.		Test Chip Restrictions
D.1		No right is granted to LICENSEE to distribute or commercially exploit the Test Chips, or any technology contained therein (excluding the ARM Compliant Core) without obtaining a separate licence from ARM.
E.		IP access model Provisions
		Number of Unique ARM Compliant Products
E.1		Under this Annex 1, LICENSEE shall have the right to exercise the licenses granted under Clause B.1 of this Annex 1 for an unlimited number of Unique ARM Compliant Products, provided that for each such Unique ARM Compliant Product LICENSEE pays to ARM the respective Use Fee as set out in, and in accordance with the provisions of Section 8 of this Annex 1.
		Audit
E.2		In addition to the audit requirements in Clause 6.6 of the TLA, the Auditors shall be entitled to review; (i) the ARM Technology which has been Downloaded by LICENSEE; (ii) Design Starts for any Unique ARM Compliant Products; and (iii) any information necessary to substantiate and verify the data submitted to ARM by LICENSEE in any Usage Report provided in accordance

with Section 8. LICENSEE’s books and records relevant to verification of the information which LICENSEE is obliged to report pursuant to this Clause, shall be retained by LICENSEE for at least six (6) years after the end of the period to which the Download, Design Start or Usage Report relates.

SECTION 3 — VERIFICATION

VERIFICATION

V.1		Definitions
V.1.1		“Implementation” means, in respect of a microprocessor core, a unique physical layout for such microprocessor core.
V.1.2		“Post Layout Synthesized Netlist” means a post layout synthesized netlist incorporating the ARM Compliant Core which; (i) obeys the Timing Constraints File in respect of such synthesis; and (ii) includes back annotated delays derived from the physical layout.
V.1.3		“Timing Constraints File” means the timing constraints file determined by LICENSEE prior to final synthesis.
V.1.4		“Validation and Verification Confirmation” means the completed document in the form set out in Part D of Section 3 of this Annex 1.
V.1.5		“Validation Deliverables” means together the AVS and the Verification and Validation Environment.
V.2		Validation and Verification of ARM Compliant Core Implementation
V.2.1		For each Implementation of an ARM Compliant Core intended for incorporation in integrated circuits which will be distributed by or for LICENSEE, LICENSEE shall verify such Implementation by at least one of the following methods;

	1.		Validation and verification by Equivalence Checking of RTL and Synthesized Netlist (See Part A)
	2.		LICENSEE Specified validation and verification (See Part B)
	3.		Validation and verification by Test Chip (See Part C)

Part A

Validation and verification by Equivalence Checking of RTL and Synthesized Netlist

Methodology

Validation

V.A.1

Validate the configured Synthesisable RTL using the Validation Deliverables in accordance with the Implementation and Integration Documentation and generate the validation log report (“Validation Logs”).

Verification

V.A.2

(i) use an equivalence checker to compare the Synthesisable RTL with the Post-Layout Synthesized Netlist and generate equivalence check log results (“RTL-Post Layout Equivalence Log Results”); (ii) simulate the Functional Test Vectors on the Post-Layout Synthesized Netlist and generate log results (“Post Layout Log Results”); and (iii) run static timing analysis on the Post-Layout Synthesized Netlist and generate log results (“STA Log Results”).

Delivery of Validation and Verification Confirmation

V.A.3

If the Validation Logs, RTL-Post Layout Equivalence Log Results, Post Layout Log Results and the STA Log Results (together the “Equivalence Log Results”) indicate that no errors have been detected (or the parties have jointly agreed a waiver in respect of any detected errors), LICENSEE shall deliver a Verification Confirmation to ARM and ARM shall acknowledge, in writing, the receipt by ARM of the Verification Confirmation within ten (10) working days of its receipt by ARM.

Validation and Verification Criteria

V.A.4

The Implementation of the ARM Compliant Core shall be validated and verified when; (i) the Equivalence Log Results indicate that no errors have been detected (or the parties have jointly agreed a waiver in respect of any detected errors); and (ii) LICENSEE has received confirmation of receipt of the relevant Validation and Verification Confirmation from ARM in accordance with the provisions of Clause V.A.3.

Records and Delivery of Equivalence Log Results

V.A.5

For each ARM Compliant Product incorporating an Implementation of the ARM Compliant Core, LICENSEE shall keep a copy of the Equivalence Log Results for such ARM Compliant Product and shall deliver, as soon as reasonably possible, copies of such records to ARM upon request from ARM. If ARM concludes that the Implementation of the ARM Compliant Core has not been validated and verified in accordance with the provisions of Clause V.A.4, then ARM shall indicate to LICENSEE the errors which ARM has detected and LICENSEE shall repeat the process prescribed in Clauses V.A.1-V.A.3.

Part B

LICENSEE Specified Validation and Verification

Methodology

V.B.1		Subject to V.B.4, use LICENSEE’s custom validation and verification flow.
V.B.2		If LICENSEE elects such validation and verification, LICENSEE shall, inform ARM in writing at least ninety (90) days prior to tape out of an ARM Compliant Product that LICENSEE wishes to use LICENSEE’s specified validation and verification flow and supply to ARM a copy of the proposed validation and verification flow (each a “Validation and Verification Flow”). Within 30 days of the receipt of the Validation and Verification Flow ARM shall notify LICENSEE in writing whether the Validation and Verification Flow has been accepted by ARM. If accepted by ARM, LICENSEE shall validate and verify such ARM Compliant Products using the Validation and Verification Flow. If after acceptance of the Validation and Verification Flow by ARM, LICENSEE wishes to modify the Validation and Verification Flow LICENSEE shall submit the modified Validation and Verification Flow to ARM for re-acceptance prior to validating and verifying the relevant Synthesisable ARM Compliant Core.
V.B.3		If ARM rejects either the Validation and Verification Flow or any modified Validation and Verification Flows, ARM shall provide LICENSEE with written reasons for such rejection together with any required changes. LICENSEE may resubmit the Validation and Verification Flow or any modified versions thereof to ARM for acceptance.

Default

V.B.4

If ARM fails to accept the Validation and Verification Flow LICENSEE shall validate and verify the Post Layout Synthesized Netlist in accordance with one of the other methods set out in Clause V.2.1.

Part C

Validation and verification by Test Chip

Methodology

Validation

V.C.1

Validate the configured RTL using the Validation Deliverables in accordance with the Implementation Guide and generate the validation log report (“Validation Logs”).

Verification

V.C.2

Design (or have designed) and manufacture (or have manufactured) a Test Chip and run on such test chip; (i) the Test Chip Functional Test Vectors to generate a results log (“Test Chip Test Vector Log Results”).

Delivery of Test Chips

V.C.3

After the Test Chip Test Vector Log Results indicate that no errors have been detected (or the parties have jointly agreed in good faith, a waiver in respect of any errors), LICENSEE shall deliver the Test Chip Test Vector Log Results and five (5) tested samples of the Test Chip to ARM. As soon as reasonably possible following receipt by ARM of the five (5) test chip samples, ARM shall run the test chip silicon validation software to generate a results log (“Test Chip Validation Log Results”) and provide to licensee (i) notice of verification of the Implementation in accordance with the provisions of Clause V.C.4 or (ii) error logs of any verification failures.

Validation and Verification Criteria

V.C.4

The ARM Compliant Core shall be verified when; (i) the Validation Logs indicate that no errors have been detected (or the parties have jointly agreed a waiver in respect of any detected errors); and (ii) the Test Chip Test Vector Log Results for the Implementation indicate that no errors have been detected (or the parties have jointly agreed a waiver in respect of any detected errors); and (iii) LICENSEE has received notice of verification of the Implementation from ARM in accordance with the provisions of Clause V.C.5.

Notice of Validation and Verification

V.C.5

ARM shall notify LICENSEE, in writing, within thirty (30) days of delivery by LICENSEE of the Test Chip samples to ARM, whether such Test Chip has been verified or has failed the validation and verification process. In the event that any Test Chip fails the process, ARM shall provide details of the errors that cause the failure to LICENSEE and LICENSEE shall endeavour to correct the errors. The parties shall repeat the above process until either; (i) the Test Chip is validated and verified; or (ii) LICENSEE withdraws the Test Chip from the validation and verification process. In the event that ARM fails to report the result of the validation and verification process within the Verification Period, the Test Chip subject to the verification process shall be deemed verified.

Part D

Validation and Verification Confirmation

Validation and Verification in accordance with Section 3 Part A

1.

Equivalence checking

Description of process applied		Tool(s) used				Completed (Tick)
ARM Compliant Core RTL to post-layout netlist *

* Process can be performed in one step or using several intermediate steps

2.

STA on Post-Layout Synthesized Netlist

Description of process applied		Tool(s) used				Completed (Tick)
Post-layout netlist

3.

Test Vector Simulations on Post-Layout Synthesized Netlist

Description of process applied		Tool(s) used				Completed (Tick)
Functional Test Vectors (file names)

Verification in accordance with Section 3 Part B

Depending upon agreed verification methodology.

Partner
Partner Contact
Core Name and Revision
Date
Signature

SECTION 4 — SUPPORT LIMITATION

4.1		Except as provided below, the maximum number of man hours that ARM shall be obligated to expend on any individual support case submitted to ARM by LICENSEE shall be capped at sixteen (16).
4.2		If ARM reasonably believes that any individual support case will exceed the support cap referred to above, ARM and LICENSEE will mutually agree a plan of action for resolution of the support case.
4.3		If a support case results in a defect being identified, any time associated with correcting such defect will not be logged against such support case.
4.4		If ARM, at ARM’s discretion, determines that LICENSEE has entered multiple cases which relate to the same support problem, ARM shall be entitled to compile these into a single case which in aggregate will be subject to the cap referred to above.
4.5		If ARM agrees to provide support at LICENSEE’s premises in accordance with the provisions of Clause 7.3 of the TLA, any time spent at LICENSEE’s premises including travel shall not be included as part of the support cap.

SECTION 5 — TRAINING REQUIREMENT

Subject to the payment of the Training Fee (set out in Section 8 of this Annex 1), ARM shall make available the following training to LICENSEE

		Commencement		Course Length				Number of Permitted
Training Course		Date		(Days)				Trainees
ARM*** IMPLEMENTATION COURSE		within 6 months of Effective Date		2				12

SECTION 6 — TRADEMARKS

		Trademark		Registered/ Unregistered
Part A
		ARM w/bar [logo] Exhibit A		Registered
Part B
		ARM Powered [logo] Exhibit B		Registered
Part C
		ARM [logo] Exhibit C		Registered
Part D
		ARM Connect Community Partner [logo] Exhibit D		Unregistered
Part E
		ARM		Registered
		ARM***		Unregistered

SECTION 7 — TERM

Unless terminated earlier in accordance with the provisions of Clause 14 of the TLA, this Annex 1 shall continue in force for a period of four (4) years.

SECTION 8 — FEES AND ROYALTIES

“Product Annexes” means the following Annexes:

	(i)		ARM*** Annex (document reference LEC-ANX-01730);
	(ii)		ARM7TDMI-S Annex (document reference LEC-ANX-01731);

PRE-PAID LICENCE FEE

In consideration of ARM delivering the ARM Technology licensed under the Product Annexes to LICENSEE, LICENSEE shall pay to ARM a non-refundable, pre-paid license fees in accordance with the table set out below:

		US$
Fee (Descriptor)		Due		Payable		Due Date (Invoice Date)
Pre-Paid Licence Fee		***
				***		Annex Effective Date
				***		Within 5 months of Annex Effective Date
Training Fee		***		***		Annex Effective Date

Use Fees

Subject to the provisions of this Section 8, for each Unique ARM Compliant Product developed under this Annex 1, LICENSEE shall pay to ARM the relevant Use Fees set out in the table below for each ARM Compliant Core contained within such Unique ARM Compliant Product:-

ARM Technology		Use Fee (US$)
Each ARM Compliant Product containing ARM*** core		$***

The Use Fee payable to ARM by LICENSEE shall be due to ARM as follows:-

	•		Upon first Download of the ARM Technology, in respect of the first Unique ARM Compliant Product;
	(iii)		Upon Design Start of the second and each subsequent Unique ARM Compliant Product

All Use Fees shall be due at the end of the Quarter in which the Download or Design Start has occurred as applicable. Notwithstanding the foregoing, LICENSEE shall not be obligated to pay the whole or any part of any Use Fees to ARM under the Product Annexes, until such time as the aggregate Use Fees which LICENSEE is obligated to pay to ARM under the Product Annexes has exceeded the amount of the Pre-Paid License Fee stated above.

Access Fee

In consideration of ARM making the products licensed under the Product Annexes available to LICENSEE for Download, LICENSEE shall pay to ARM an annual fee in accordance with the following table (“Access Fee”)

Fee		Description		Support & Maintenance Fees (US$)
Access Fee		All ARM Technology licensed under the Product Annexes		$***

LICENSEE shall pay each Access Fee to ARM as follows:-

	•		In respect of the first year of the Term, the Access Fee is included in the Pre-Paid License Fee set out above;
	(iv)		subject to request from LICENSEE in respect of each subsequent year of the Term, upon each anniversary of the Annex Effective Date

Support and Maintenance

		Support and Maintenance Fees
Product(s)		Year 1*		Year 2**		Year 3***		Year 4****
ARM***		***		***		***		***

Access to ARM Technology

Subject to and in consideration of the payment of the Access Fee in accordance with the provisions of this Section 8, ARM shall make the ARM Technology available to LICENSEE for Download.

Usage Report

LICENSEE shall submit to ARM a report (each a “Usage Report”) within thirty (30) days after the end of every Quarter. Each Usage Report shall contain the following information relating to each ARM Compliant Product and which shall be substantially in the form set out below.

Part

Number of

Unique

ARM

Support and

ARM

Date of

Date of

Compliant

Maintenance

Technology

Download

Design Start

Product

Use Fee

Fee

Fees Due

ROYALTIES

For the purposes of the Royalty tables,

“Handset Baseband” means a baseband processing device which (i) includes an ARM Core; and either or both (ii) supports the protocol and signal processing functions of a wireless cellular communications standard, including but not limited to standards, GSM, GPRS, EDGE, CDMA, WCDMA and TD-SCDMA and any combinations thereof, and (iii) an applications processor for a mobile phone or PDA running an operating system including but not limited to Windows CE, Pocket PC, SymbianOS, PalmOS, or Linux.

“Bluetooth” means the connection and exchange of information between one device and other devices using a secure globally unlicensed short range radio frequency and which conforms to the industrial specification for wireless personal networks known as “Bluetooth”.

Currency:		US Dollars
Currency Conversion:		ASP in any currency other than US$shall be converted to ASP in US$ using the average local currency/US$ exchange rate over the Quarter as published by the US Federal Reserve [see ▇▇▇▇://▇▇▇.▇▇▇▇▇▇▇▇▇▇▇▇▇▇.▇▇▇/▇▇▇▇▇▇▇▇/▇▇/]
Due:		At the end of each Quarter
Payable:		In accordance with the provisions of Clause 6 of the TLA.
Invoice Address:		▇▇▇▇, ▇▇/▇ ▇▇▇▇▇ Merchants Tower, ▇▇▇ ▇▇▇▇▇▇▇▇▇ ▇▇▇▇ ▇▇▇▇▇▇▇, ▇▇▇▇ ▇▇▇▇

Calculation:

For each unit of ARM Compliant Product distributed by LICENSEE, LICENSEE shall pay a Royalty calculated by multiplying the ASP for the ARM Compliant Product by the Royalty Rate determined from the following table:

For Bluetooth products:-

Cumulative Number of Units of ARM Compliant
Products distributed by LICENSEE		Royalty Rate
***		***% ASP
***		***% ASP
***		***% ASP
***		***% ASP

For Handset Baseband products:-

Cumulative Number of Units of ARM Compliant
Products distributed by LICENSEE		Royalty Rate
***		The greater of ***% ASP and Royalty Floor*
***		The greater of ***% ASP and Royalty Floor*
***		The greater of ***% ASP and Royalty Floor*
***		The greater of ***% ASP and Royalty Floor*

For all other products:-

Cumulative Number of Units of ARM Compliant
Products distributed by LICENSEE		Royalty Rate
***		The greater of ***% ASP and Royalty Floor**
***		The greater of ***% ASP and Royalty Floor**
***		The greater of ***% ASP and Royalty Floor**
***		The greater of ***% ASP and Royalty Floor**

**		Royalty Floor for the table above means :-		(i) $*** where the ASP is ³ $2;
				(ii) $*** where the ASP < $2 and ³ $1; and
				(iii) $*** where the ASP is < $1.

For the purpose of calculating Royalties, only the distribution by the entity exercising the licences to distribute encapsulated die of ARM Compliant Products which have been manufactured under this Annex 1 (notwithstanding that such distribution may be between RDA and a Subsidiary of RDA or between Subsidiaries of RDA) shall be relevant.

All Royalties paid to ARM pursuant to this Annex 1 shall be non refundable.

In an ARM Compliant Product with more than one ARM core embedded into the same piece of silicon, the royalties for each core in the device shall be cumulated up to a maximum number of five cores in total, starting with the cores that have the highest royalty. The total royalty payable on the second and subsequent cores in accordance shall be reduced in accordance with the following table;

Core		% of royalty payable
ARM core with highest royalty		***% of applicable Royalty
ARM core with same or second highest royalty		***% of applicable Royalty
ARM core with same or third highest royalty		***% of applicable Royalty
ARM core with same or fourth highest royalty		***% of applicable Royalty
ARM core with same or fifth highest royalty		***% of applicable Royalty

Example 1:

An ARM Compliant Product contains three ARM*** Cores, the ASP of the ARM Compliant Product is US$*** and the royalty payable on the cumulative volume is ***% ASP subject to a floor of US$***.

Total Royalty = US$*** (floor amount) + ($***x*** – for second core) + ($***x*** – for third core) = US$***

Example 2:

An ARM Compliant Product contains three ARM*** cores with an applicable royalty rate of 3% and three ARM***cores with an applicable royalty rate of ***% subject to a floor of US$***. The ASP of the ARM Compliant Product is US$10. Since there are 6 cores, only the first five are counted for royalty generating purposes.

Total royalty = ($***x***% for *** core) + ($***x***x*** – for second *** core) + ($***x***%x*** for third *** core) + ($***x*** – fourth core (floor applies)) + ($***x*** – fifth core (floor applies)) = US$***

ROYALTY REPORT

Form of Royalty Report

Send to:		The address for ARM set out in the TLA via first class mail and to ▇▇▇▇▇▇▇▇▇▇▇▇▇▇@▇▇▇.▇▇▇ via email.

LICENSEE

LICENSEE contact

Quarter for which report relates to                                                                           

Table 1

				Number of Units of
				ARM Compliant
				Product distributed
Part		Intended		by LICENSEE in				Applicable Royalty
Number		Application		Quarter		ASP (US$)		Rate		Royalty Due
						$XXX		X%		$XXX
						$XXX		X%		$XXX

Table 2

				Estimated Number of
				Units of ARM
				Compliant Product
				distributed by
Part		Intended		LICENSEE in Next				Applicable Royalty
Number		Application		Calendar Quarter		ASP (US$)		Rate		Royalty Due
						$XXX		X%		$XXX
						$XXX		X%		$XXX

The information provided in Table 2 shall be non-binding, supplied in good faith and treated as LICENSEE’s Confidential Information.

SECTION 9 — MARKETING

Notwithstanding anything to the contrary contained in the TLA either party may disclose to third parties that LICENSEE is a licensee of the ARM Technology licensed under this Annex 1. Except as expressly provided in the TLA, no right is granted to either party to disclose the terms and conditions of the TLA or this Annex 1.

Within sixty days (60) days of the Annex Effective Date the parties shall mutually agree the terms and method of issuance of a written announcement, which may be a press release, relating to the technology licensed under this Annex 1 and the relationship of the parties.

All communications for the above marketing activities shall be sent to the following contacts

ARM Marketing Contact		LICENSEE Marketing Contact
Director of Corporate Communications		▇▇▇▇▇▇▇ ▇▇▇
		▇▇▇▇▇▇▇▇▇▇@▇▇▇▇▇▇▇▇.▇▇▇
▇▇▇▇▇▇▇▇▇▇▇▇▇@▇▇▇.▇▇▇		3328, 33/F China Merchants Tower,
▇▇▇ ▇▇▇▇▇▇▇▇ ▇▇▇▇		▇▇▇ ▇▇▇▇▇▇▇▇▇ ▇▇▇▇ ▇▇▇▇▇▇▇,
Cambridge		Hong Kong
CB1 9NJ

SECTION 10 — END USER LICENCE

[Respective LICENSEE entity] (“LICENSOR”) hereby grants and the LICENSEE hereby accepts a non transferable and nonexclusive licence to use the Model solely for the purpose of developing a product which incorporates a CPU manufactured under LICENSOR’s licence from ARM (“Purpose”), under the following terms and conditions:

1.

Ownership. The Model is the property of ARM LIMITED and/or its licensors. The LICENSEE acquires no title, right or interest in the Model other than the licence rights granted herein.

2.

Use. The LICENSEE may use the Model on any one computer at one time except that the Model may be executed from a common disc shared by multiple CPUs provided that one authorised copy of the Model has been licensed from LICENSOR for each CPU concurrently executing the Model.

LICENSEE shall not reverse engineer, decompile or disassemble the Model, in whole or in part.

LICENSEE shall only be permitted to use the Model for the Purpose.

LICESENSOR hereby authorises LICENSEE to concurrently use up to a maximum number of [  ] copies of the Model.

3.

Copies. Except as provided in Clause 2, LICENSEE may make copies of the Model for back-up and archival purposes only. All copies of the Model must bear the same notice(s) contained on the original copies supplied by LICENSOR.

4.

Model Limited Warranty. LICENSOR warrants that the disks containing the Model shall be free from defects and workmanship under normal use and the programs will perform in accordance with the accompanying documentation for a period of ninety (90) days from the date of delivery. Any written or oral information or advice given by LICENSOR distributors, agents or employees will in no way increase the scope of this warranty. LICENSOR’s entire liability and the LICENSEE’s exclusive remedy will be, at LICENSOR’s sole option, to replace the disk or to use LICENSOR’s reasonable efforts to make the Model meet the warranty set forth above. Any replacement Model will be warranted for the remainder of the original warranty period or thirty (30) days, whichever is the longer. The LICENSEE agrees that the supply of the Model does not include updates and upgrades, which may be available from LICENSOR under a separate support agreement.

THE ABOVE WARRANTIES ARE EXCLUSIVE AND IN LIEU OF ALL OTHER WARRANTIES, WHETHER EXPRESS OR IMPLIED INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

IN NO EVENT SHALL LICENSOR BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES RESULTING FROM ITS PERFORMANCE OR FAILURE TO PERFORM UNDER THIS AGREEMENT OR THE FURNISHING, PERFORMANCE, OR USE OF ANY MODEL LICENSED HERETO, WHETHER DUE TO BREACH OF CONTRACT, BREACH OF WARRANTY, OR NEGLIGENCE EVEN IF LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

THE MAXIMUM LIABILITY OF LICENSOR SHALL BE LIMITED TO REFUND OF THE FEES PAID BY LICENSEE (IF ANY) FOR THE MODEL.

5.

Assignment of the Agreement. This Agreement and any license granted hereunder to the LICENSEE may not be assigned, sub-licensed or otherwise transferred by the LICENSEE to any third party.

6.

Term and Termination. Unless terminated in accordance with the provisions of this Clause 6, this Agreement and licenses granted hereunder shall continue in force until completion of the Purpose. LICENSOR may terminated this Agreement by written notice to the LICENSEE in the event of a breach by LICENSEE of any provisions of this Agreement.

Upon expiration or termination of this Agreement, the LICENSEE shall refrain from any further use of the

Model, and LICENSEE shall either return or destroy and copies of the Model in it’s possession at the date of expiration of termination as applicable.

7.

Applicability. The limitations and exclusions above may not apply in certain countries or states where they conflict with local law. In cases where such a conflict exists the local law shall prevail and the remaining provisions of the Agreement shall remain in full force and effect.

IN WITNESS WHEREOF the parties have caused this Annex 1 to be signed by their duly authorised representative:

ARM LIMITED				RDA INTERNATIONAL INC.
BY:		/S/ ▇▇▇▇▇▇ ▇▇▇▇▇		BY:		/s/ ▇▇▇▇ ▇▇▇▇
NAME:		▇▇▇▇▇▇ ▇▇▇▇▇		NAME:		▇▇▇▇ ▇▇▇▇
TITLE:		General Counsel		TITLE:		CFO
DATE:		8 July 2009		DATE: