Contract Number 81163-PPCG
14 March 2000
EXHIBIT 10.15
[*] DEVELOPMENT AGREEMENT
BETWEEN
TYCO SUBMARINE SYSTEMS LTD
AND
MULTILINK TECHNOLOGY CORPORATION
THIS DEVELOPMENT AGREEMENT ("Agreement"), is made effective September 1,
1999 ("Effective Date") by and between Tyco Submarine Systems Ltd. having an
office at Patriot's Plaza, ▇▇ ▇▇▇▇▇▇▇▇ ▇▇▇▇▇▇▇▇-▇▇▇▇▇▇▇▇ ▇, ▇▇▇▇▇▇▇▇▇▇, ▇▇▇
▇▇▇▇▇▇ ▇▇▇▇▇ (hereinafter referred to as "TSSL"), and Multilink Technology
Corporation having an office at ▇▇▇ ▇▇▇▇▇▇ ▇▇▇▇▇, ▇▇▇▇▇▇ ▇▇▇▇▇, ▇▇▇▇▇▇▇▇, ▇▇,
▇▇▇▇▇ (hereinafter referred to as "Supplier").
WITNESSETH
WHEREAS, TSSL is in the business of designing, constructing and maintaining
integrated optical fiber submarine cable systems and Supplier is in the business
of designing, developing, and manufacturing integrated circuits and circuit
boards; and
WHEREAS, TSSL desires to engage Supplier for the design and development of
custom integrated circuit(s) ("Device(s)") and board assembly (ies)
("Board(s)"); and
WHEREAS, Supplier has developed design tools and design platforms
(hereinafter collectively referred to as ("Supplier Products") which, along with
compatible software and hardware, facilitate the design of Devices and Boards;
and
WHEREAS, TSSL and Supplier desire to enter into a definitive agreement for
design and development services, prototypes and production pricing to be
provided by Supplier.
NOW, THEREFORE, TSSL and Supplier, in consideration of the mutual promises
set forth herein and for other good and valuable consideration hereby agree as
follows:
ARTICLE 1 - STATEMENT OF WORK
Supplier shall render to TSSL all the technical and manufacturing services for
the design, development, prototype fabrication and test ("Work") of the Devices
and the Boards as specified in the attached Exhibits.
Supplier shall complete such Work within the time allowed in this Agreement, and
shall meet all interim deadlines, as specified in Exhibit C. The Work shall meet
all required specifications and test requirements stated herein, shall be
performed in accordance with the highest standards and shall be in accordance
with such requirements or restrictions as may be lawfully imposed by
governmental authority.
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
TSSL Proprietary
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Contract Number 81163-PPCG
14 March 2000
ARTICLE 2 - EXHIBITS
The following Exhibits have been attached hereto and are hereby incorporated by
reference herein: Exhibit A - Statement of Work
Exhibit B - Specifications
Exhibit C - Schedule
ARTICLE 3 - NOTICES
Any notice or demand required to be given or made by Supplier or TSSL shall be
in writing and shall be given or made by confirmed facsimile or similar
communication or by certified or registered mail addressed as follows:
To TSSL: ▇▇▇ ▇▇▇▇▇▇▇
Tyco Submarine Systems Ltd.
Room 3A-241
60 Columbia Turnpike - Bldg. A
▇▇▇▇▇▇▇▇▇▇, ▇▇▇ ▇▇▇▇▇▇ ▇▇▇▇▇
To Multlink: ▇▇▇▇▇ ▇▇▇▇
Multilink Technology Corporation
▇▇▇ ▇▇▇▇▇▇ ▇▇▇▇▇, ▇▇▇▇▇▇ ▇▇▇▇▇
▇▇▇▇▇▇▇▇, ▇▇ ▇▇▇▇▇
ARTICLE 4 - REPRESENTATIVES
TSSL's Technical Representative is [*] (Telephone [*] ), TSSL's
Component Engineer is [*] (Telephone [*] ) and TSSL's
Agreement Representative is [*] (Telephone [*] ), or such other
persons as may be designated in writing by TSSL from time to time. Multilink's
Technical Representative is [*] (Telephone [*] ), and Product
Line Manager is [*] (Telephone [*] ) and Agreement
Representative is [*] (Telephone [*] ), or such other
persons as may be designated in writing by Multilink from time to time.
ARTICLE 5 - DELIVERY SCHEDULE
5.1 The Supplier shall meet the following Milestones:
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Task Milestone Required Delivery Late Delivery
Date Date
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[*] Preliminary Design Review 9/6/99 - Complete
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[*] Critical Design Review 12/6/99 - Complete
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[*] Preliminary Design Review 12/14/99 - Complete
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[*] Prototype Delivery 1/30/00 - Complete
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[*] Final Data Review 3/3/00
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[*] Delivery (2 each) 3/21/00 3/21/00
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[*] Delivery (2 each) 3/21/00 3/21/00
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Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
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Contract Number 81163-PPCG
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[*] Delivery ([*] each) 3/24/00 3/29/00
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[*] Delivery ([*] each) 3/24/00 3/29/00
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[*]
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[*] Delivery ([*] each) 4/1/00 - 4/28/00
Delivered Weekly
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[*] Delivery ([*] each) 6/16/00-7/16/00
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The Delivery Date is defined as the date that the Supplier ships from the
factory for overnight next day delivery to TSSL.
The delivery dates for the prototypes are as stated in the "Required Delivery
Dates" column. The date stated in the "Late Delivery Date" column will be used
to determine the price reduction for late delivery in accordance with 5.2 and
Article 7.
5.2 The Supplier shall be entitled to receive an Incentive Payment for the
early delivery of the Prototype Sets.
[*]
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Early delivery is defined as meeting a delivery date of 3/21/00 for the Set for
which the Supplier shall receive an incentive payment of $100,000.
[*]
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Early delivery is defined as meeting a delivery date of 3/24/00 for supplying
the Set with the [*] having the reverse bit order and for supplying the
[*] with the required bit order by 3/29/00. If the Supplier meets
both these dates the Supplier will be entitled to receive a $50,000 incentive
payment.
If the Supplier meets a delivery date of 3/24/00 for supplying the Set with the
[*] having the required bit order, the Supplier shall be entitled to
a $100,000 incentive payment.
ARTICLE 6 - PROTOTYPE PRICING
Supplier will be paid the following unit price for each of the Prototypes
delivered in accordance with Article 5:
Additional
Board Prototype Prices
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[*] $ [*]
[*] $ [*]
[*] $ [*]
[*] $ [*]
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
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14 March 2000
ARTICLE 7 - PRODUCTION PRICING
7.1 The Supplier has agreed to the production pricing as follows:
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Board/Quantity First 200* 201 - 1000** 1001 - 1500
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[*] [*] [*] [*]
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[*] [*] [*] [*]
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[*] [*] [*] [*]
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[*] [*] [*] [*]
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Total Set Price [*] [*] [*]
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*Prices are based on the 1000 piece order commitment.
** Includes First 200
The "Required Prototype Delivery Dates" are as stated in Article 5. The
Production Pricing for the first quantity of 200, which includes the Models
quantity, is based on the Supplier meeting the Required Prototype Delivery
Dates for the first two sets of boards, with the sets of boards as defined in
Article 5. If the Supplier does not meet the Required Prototype Delivery Dates
for the first two sets of boards, the Production Pricing stated for the first
quantity of two hundred shall be reduced on a pro-rated basis based on the
number of days missed between the Required Prototype Delivery Dates for the
first two sets of boards and the date of April 7, 2000, the "Late Delivery
Date". Each board within a Set shall be reduced for the first quantity of two
hundred (200) at the per business day rate as follows:
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BOARD PRICE REDUCTION BY
BOARD BY DAY
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[*] [*]
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[*] [*]
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[*] [*]
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[*] [*]
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7.2 The Production Pricing at the 1000 piece quantity includes a Value
Engineering Investment of $400,000 by the Supplier. This investment is
reflected in the reduced price that TSSL will pay for each item from the
quantity of 750 to 1000 piece quantities as stated above. Should TSSL not take
delivery of the quantity of 1000, then TSSL will be required to reimburse the
Supplier for the prorated amount of the investment between the quantity
delivered and the quantity of 1000. For example, if TSSL takes delivery of a
quantity of 850, TSSL will be required to reimburse the Supplier for sixty (60)
per cent of the $400,000 (1000 - 850 = 150 which is 60% of 250).
The Production Pricing and Value Engineering Investment terms stated above
shall be applicable to and be made a part of the Supply Agreement that will be
entered into between
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
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Contract Number 81163-PPCG
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Supplier and TSSL's Exeter Manufacturing Center located in Exeter, NH, which
agreement shall include the terms and conditions similar to those as stated in
the current Supply Agreement.
ARTICLE 8 - PERIOD OF PERFORMANCE
The Supplier shall comply with the schedule for the design, development, and the
fabrication and delivery of the Prototypes, which shall be completed no later
than April 7, 200O.
The delivery of the Models shall be made beginning June 16, 2000 through July
16, 2000. The quantities and specific delivery dates of the quantities will be
mutually agreed to between the Parties, but it is expected that the quantity
will be between [*] and [*] .
In the event of a conflict between Article 5 Delivery Schedule and Exhibit C,
Article 5 shall take precedence.
ARTICLE 9 - VERSION 3 DISCUSSIONS
TSSL and the Supplier will initiate discussions on Supplier's possible
participation in TSSL's Version 3 HPOE Program.
ARTICLE 10 - ACCEPTANCE
TSSL shall have the right to evaluate all Work for compliance with the
Specifications. Supplier shall provide TSSL with free access to the Work
performed and the items furnished under this Agreement, for the purpose of
inspection thereof. At any time during the progress of the Work, TSSL may reject
any or all of the Work if the same are not in accordance with this Agreement,
and shall give written notice to Supplier of such non-compliance. Supplier
agrees to correct, at its expense, each error or defect (referred to herein
collectively as "defect") leading to such rejection and resubmit to TSSL within
seven (7) business days, or other mutually agreed upon date, after receipt of
notice from TSSL of such error or defect.
ARTICLE 11 - INVOICING
Supplier's invoices shall be rendered upon documented completion and acceptance
of a Milestone and for hardware deliveries, after delivery of the Boards
provided for in this Agreement; and shall be payable net thirty (30) days from
the receipt of the invoice. For all payments Supplier shall reflect the Purchase
Order Number, and shall be submitted in duplicate to:
TYCO Submarine Systems Ltd
▇▇▇ ▇▇▇▇▇▇ ▇▇▇▇▇
▇▇▇▇▇▇, ▇▇ ▇▇▇▇▇-▇▇▇▇
Attn: Accounts Payable Department
Supplier shall mail invoices with copies of any supporting documentation
required herein. The Work shall be delivered free from all claims, liens, and
charges whatsoever. TSSL
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
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Contract Number 81163-PPCG
14 March 2000
reserves the right to require before making payment, proof that all parties
furnishing labor and materials for the work have been paid.
ARTICLE 12 - PAYMENT TERMS
Unless payment terms more favorable to TSSL appear on Supplier's invoice and
TSSL elects to pay on such terms, invoices shall be paid in accordance with the
terms stated in this Agreement, and due dates for payment of invoices shall be
computed.from the date of receipt of invoice by TSSL.
ARTICLE 13 - TITLE TO MATERIAL; RISK OF LOSS
Unless otherwise specified herein, title and risk of loss or damage to the Work,
shall remain with Supplier until the Work is accepted for delivery by TSSL at
the point of origin specified herein. Notwithstanding the above, if in any case
TSSL pays Supplier for any Work prior to TSSL's acceptance for delivery, title
to such Work shall vest in TSSL upon payment of the applicable invoice, but risk
of loss and damage shall remain with Supplier and shall pass to TSSL only upon
acceptance for delivery by TSSL. Acceptance for delivery involves the acceptance
for physical delivery and in no way affects acceptance of the Work with respect
to conformance with the Exhibits.
ARTICLE 14 - ASSIGNMENT AND SUBCONTRACTING
Supplier shall not assign any right or interest under this Agreement (excepting
moneys due or to become due) or delegate or subcontract any Work (except as
stated herein) or other obligation to be performed or owed under this Agreement
without the prior written consent of TSSL. Any attempted assignment, delegation
or subcontracting in contravention of the above provisions shall be void and
ineffective. Any assignment of moneys shall be void and ineffective to the
extent that (1) Supplier shall not have given TSSL at least thirty (30) days
prior written notice of such assignment or (2) such assignment attempts to
impose upon TSSL obligations to the assignee additional to the payment of such
moneys, or to preclude TSSL from dealing solely and directly with Supplier in
all matters pertaining to this Agreement including the negotiation of amendments
or settlements of charges due. All Work performed by Supplier's subcontractor(s)
at any tier shall be deemed Work performed by Supplier.
ARTICLE 15 - QUALITY SYSTEM AUDIT
15.1 If requested, Supplier agrees to permit TSSL or its agent to conduct an
initial and any subsequently required on-site Quality System Audit(s) (QSA) of
Supplier's Quality System at TSSL's expense. Such an audit shall assess the
effectiveness and documentation of the various elements that comprise a
functioning quality system which may include, but not be limited to the
following elements:
A) Management Responsibility
B) Quality System
C) Contract Review
D) Design Control
E) Document & Data Control
TSSL Proprietary
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F) Purchasing
G) Control of TSSL Supplied Equipment
H) Equipment Identification and Traceability
I) Process Control
J) Inspection and Testing
K) Control of Inspection, Measuring and Test Equipment
L) Inspection and Test Status
M) Control of Non-conforming Equipment
N) Corrective Action and Preventive Action
0) Handling, Storage, Packaging, Preservation, and Delivery
P) Control of Quality Records
Q) Internal Quality Audits
R) Training
S) Servicing
T) Statistical Techniques
15.2 Supplier further agrees that any deficiencies discovered in Supplier's
quality system as a result of the audit(s) shall be reviewed and agreed to by
Supplier. Necessary remedies shall be as agreed to by the Parties and shall be
implemented to the satisfaction of all Parties. Remedies shall be implemented at
no additional cost to TSSL.
15.3 Upon written request and at no additional charge, Supplier agrees to
provide TSSL with a written description of its Quality Plan for the Equipment
used in undersea cable systems. Said Quality Plan description shall be provided
to TSSL in the English language.
ARTICLE 16 - IS0 9000
16.1 TSSL is an IS0 9001: 1994 Certified Company. It is, therefore, a
requirement that each Supplier and sub-Supplier to TSSL either be IS0 9000
Certified, or, if not IS0 9000 Certified, that Supplier and sub-Supplier
document to TSSL that they have in place a Quality System and Quality Plan.
These IS0 9000 certifications or other Quality System(s) and Quality Plan(s)
must be submitted to TSSL for review and approval, prior to the issuance of any
Order by TSSL for Equipment(s). Supplier and sub-Supplier must indicate their
willingness to be audited by TSSL or TSSL's representative(s) for compliance
with IS0 9000 or Supplier's and sub-Supplier's own Quality System(s) and Quality
Plan(s).
16.2 If Supplier or sub-Supplier is IS0 9000 certified, Supplier shall, prior to
or upon execution of this Agreement, provide TSSL's representative indicated
below a copy of the appropriate certificate(s) of registration issued by such
third party accredited registrar(s), such as the Registration and Accreditation
Board (RAB-U.S.), Royal Dutch Standards Bureau (RvA) or United Kingdom
Accreditation Society (UKAS). Supplier shall also maintain such certificate(s)
of registration through appropriate assessments by such third party accredited
registrar(s) and provide to customer's representative any applicable updated
certificate(s) or notifications of failure to pass a surveillance or full
registration audit. If Supplier or sub-Supplier fails, for any reason, to
maintain or provide to TSSL such certificate(s) of registration as set forth
above, TSSL shall have the right, and without any cost to or liability
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Contract Number 81163-PPCG
14 March 2000
or obligation of TSSL, to terminate this Agreement and any outstanding Orders
placed under this Agreement. TSSL's representative for IS0 9000 series standards
purposes is:
▇▇▇▇▇ ▇▇▇▇▇▇▇▇▇▇
TSSL
60 Columbia Turnpike-Building A
▇▇▇▇▇▇▇▇▇▇, ▇▇ ▇▇▇▇▇
▇▇▇
ARTICLE 17 - CHANGES
TSSL may at any time during the progress of the Work require additions to or
alterations of or deductions or deviations (all hereinafter referred to as a
"Change") from the Work called for by the specifications, drawings and samples.
No Change shall be considered as an addition or alteration to or deduction or
deviation from the Work called for by the specifications, drawings and samples
nor shall Supplier be entitled to any compensation for work done pursuant to or
in contemplation of a Change, unless made pursuant to a written Change Order
issued by TSSL. Within five (5) days after a request for a Change, Supplier
shall submit a proposal to TSSL, which includes any increases or decreases in
Supplier's costs or changes in the delivery or Work schedule necessitated by the
Change. TSSL shall, within ten (10) days of receipt of the proposal, either (i)
accept the proposal, in which event TSSL shall issue a written Change Order
directing Supplier to perform the Change or (ii) advise Supplier not to perform
the Change in which event Supplier shall proceed with the original Work.
ARTICLE 18 - TITLE TO MATERIAL AND LICENSES
18.1 Authorship and Copyright
All right, title and interest in and to all work and work products developed or
produced under this Agreement for TSSL, whether in the form of specifications,
drawings, sketches, models, samples, data, computer programs, documentation or
other technical or business information, and all right, title and interest in
patents, copyrights, trade secrets, trademarks and other intellectual property
derived from such work and work products are hereby assigned by Supplier to
TSSL. To the extent that such work or work products are copyrightable, they
shall be deemed to be "works made for hire" for the benefit of TSSL under the
Copyright Act.
18.2 Developed Information and Mask Work
Supplier agrees that Supplier will and, where applicable, will have Supplier
disclose and furnish promptly to TSSL any and all technical information,
computer or other apparatus programs, specifications drawings, records,
documentation, works of authorship or other creative works ideas, knowledge of
data, written, oral or otherwise expressed, originated or developed by Supplier
or by any Supplier's employees, consultants, representatives or agents
("associates") as a result of work performed under this Agreement.
TSSL Proprietary
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Contract Number 81163-PPCG
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Supplier further agrees that all such Information shall be the property of TSSL,
shall be kept in confidence by Supplier and Supplier's representatives, shall be
used only in the performance hereunder and in the filling of Orders under any
production agreement awarded by TSSL, for the manufacture of material covered
under this Agreement, and may not be used for other purposes except upon such
terms as may be agreed upon in writing by TSSL.
18.3 Inventions
Supplier agrees that if any inventions, discoveries or improvements are
conceived, first reduced to practice, made or developed in the course of, or as
a result of work done under this Agreement, by Supplier or by one or more of
Supplier's associates, Supplier will assign to TSSL and TSSL's associates entire
right, title, and interest in and to such inventions, discoveries and
improvement, and any patents that, may be granted thereon in any country of the
world.
18.4 Background Information
All right, title and interest in and to Background Information, as defined
below, shall remain the property of Supplier. "Background Information" shall
mean any information or materials previously developed or copyrighted by
Supplier, and not originated or developed as part of this Agreement, and
furnished as part of the deliverables hereunder. For purposes of this agreement,
Background Information shall include, but not be limited to, the Supplier
Products identified in Section II of the Statement of Work, titled - MULTILINK
PRODUCTS.
Supplier grants to TSSL an unrestricted, perpetual, non-exclusive, worldwide,
royalty-free, irrevocable license under copyright, mask work rights, patents
trade secrets, trade marks and other intellectual property contained in or
derived from the Background Information to use, have use, to make, have made,
reproduce, sublicense, sell, import, distribute and modify, in whole or in part,
the deliverables and Pre-existing Information and any derivative work thereof.
ARTICLE 19 - EXCLUSIVITY
Supplier shall not, without the prior written consent of TSSL, sell the Devices
or the Boards developed under this Agreement to any person or entities other
than TSSL or an associated Tyco International company for a period of ten (10)
years from the effective date of this Agreement.
ARTICLE 20 - IDENTIFICATION
Supplier shall not, without TSSL's prior written consent, engage in advertising,
promotion or publicity related to this Agreement, or make public use of any
Identification in any circumstances related to this Agreement. "Identification"
means any copy or semblance of any trade name, trademark, service ▇▇▇▇,
insignia, symbol, logo, or any other product, service or organization
designation, or any specification or drawing of TSSL or its affiliates, or
evidence of inspection by or for any of them. Supplier shall remove or
obliterate any Identification prior to any use or disposition of any material
rejected or not purchased by TSSL, and, shall indemnify, defend (at TSSL's
request) and save harmless TSSL and its
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Contract Number 81163-PPCG
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affiliates and each of their officers, directors and employees from and against
any losses, damages, claims, demands, suits, liabilities, fines, penalties and
expenses (including reasonable attorneys' fees) arising out of Supplier's
failure to so remove or obliterate.
ARTICLE 21 - IMPLEADER
Supplier shall not implead or bring an action against TSSL or its customers or
the employees of either based on any claim by any person for personal injury or
death to an employee of TSSL or its customers occurring in the course or scope
of employment and that arises out of material or services furnished under this
Agreement.
ARTICLE 22 - INDEMNITY
All persons furnished by Supplier shall be considered solely Supplier's
employees or agents, and Supplier shall be responsible for payment of all
unemployment, social security and other payroll taxes, including contributions
when required by law. Supplier agrees to indemnify and save harmless TSSL, its
affiliates, its and their customers and each of their officers, directors,
employees, successors and assigns (all hereinafter referred to in this clause as
"TSSL") from and against any losses, damages, claims, demands, suits,
liabilities, fines, penalties and expenses (including reasonable attorney's
fees) that arise out of or result from: (1) injuries or death to persons or
damage to property, including theft, in any way arising out of or occasioned by,
caused or alleged to have been caused by or on account of the performance of the
Work or services performed by Supplier or persons furnished by Supplier; (2)
assertions under Workers' Compensation or similar acts made by persons furnished
by Supplier or by any subcontractor or by reason of any injuries to such persons
for which TSSL would be responsible under Workers' Compensation or similar acts
if the persons were employed by TSSL; (3) any failure on the part of Supplier to
satisfy all claims for labor, equipment, materials and other obligations
relating directly or indirectly to the performance of the Work; or (4) any
failure by Supplier to perform Supplier's obligations under this clause or the
INSURANCE clause. Supplier agrees to participate in the defense of TSSL, at
TSSL's request, against any such claim, demand or suit. TSSL agrees to notify
Supplier within a reasonable time of any written claims or demands against TSSL
for which Supplier is responsible under this clause.
ARTICLE 23 - INFRINGEMENT
The following terms apply to any infringement, or claim of infringement, of any
patent, trademark, copyright, trade secret or other proprietary information
based on the use of any Information furnished by Supplier to TSSL under this
Agreement or in contemplation of this Agreement or order. Supplier shall
indemnify TSSL for any loss damage, expense or liability that may result by
reason of any such infrigement or claim, except where such infringement or claim
arises from Supplier's adherence to specifications or drawings which TSSL
requires Supplier to follow. TSSL, at its own expense, shall indemnify Supplier
for any loss, damage, expense or liability that may result solely by reason of
Supplier's adherence to specifications or drawings which TSSL requires Supplier
to follow.
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ARTICLE 24 - NON-SOLICITATION
Supplier agrees not to solicit for employment, directly or indirectly, any of
the Company's technical employees, which shall include any such person who has
been an employee of TSSL sixty (60) days prior to the Effective Date of this
Agreement and for a period of one (1) year subsequent to the delivery of the
Models as required in Article 8 or termination of this Agreement.
ARTICLE 25 - INSPECTION
TSSL's Representatives shall at all times have access to the Work for the
purpose of inspection or a Quality Review and Supplier shall provide safe and
proper facilities for such purpose
ARTICLE 26 - INSURANCE
26.1 Supplier shall maintain and cause Supplier's subcontractors to
maintain during the term of this Agreement the following types of insurance as
prescribed by the law of the state or nation in which the work is performed:
Supplier will name TSSL as an additional insured with waiver of subrogation with
respect to the work. All such insurance must be primary and required to respond
and pay prior to any other available coverage.
A) Workers' Compensation insurance;
B) Employer's Liability insurance, with limits of at least U.S.
$1,000,000 for each occurrence;
C) Comprehensive Automobile Liability insurance if the use of motor
vehicles is required, with limits of at least U.S. $5,000,000
combined single limit for bodily injury and property damage for each
occurrence;
D) Commercial General Liability ("CGL") insurance. The sum insured
shall be no less than U.S. $5,000,000 for any one incident, unlimited
in the aggregate;
E) If professional services are provided, Errors and Omissions
insurance in the amount of at least U.S. $5,000,000 per claim and in
the aggregate should be procured and maintained for a period of at
least one (1) year after completion of the Agreement;
F) If there is potential environmental impact or required by State
or Federal statutes, Environmental Impairment Liability (EIL or
Pollution liability) insurance in the amount of U.S. $5,000,000 for
each claim.
26.2 Supplier agrees that Supplier, Supplier's insurer(s) and anyone
claiming by, through, under or in Supplier's behalf shall have no claim, right
of action or right of subrogation against TSSL and its Customer(s) based on any
loss or liability insured against under the foregoing insurance. Supplier and
Supplier's subcontracts shall furnish prior to the start of work certificates or
adequate proof of the foregoing insurance including, if specifically
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requested by TSSL, copies of the endorsements and insurance policies. TSSL shall
be notified in writing at least thirty (30) calendar days prior to cancellation
of or any change in the policy.
ARTICLE 27 - RELEASES VOID
Neither party shall require (i) waivers or releases of any personal rights or
(ii) execution of documents which conflict with the terms of this Agreement,
from employees, representatives or customers of the other in connection with
visits to its premises and both parties agree that no such releases, waivers or
documents shall be pleaded by them or third persons in any action or proceeding.
ARTICLE 28 - RIGHT OF ENTRY AND PLANT RULES
Each party shall have the right to enter the premises of the other party during
normal business hours with respect to the performance of this Agreement, subject
to all plant rules and regulations, security regulations and procedures and US
Government clearance requirements if applicable.
ARTICLE 29 - SUPPLIER'S INFORMATION
Supplier shall not provide under, or have provided in contemplation of, this
Agreement any idea, data, program, technical, business or other intangible
information, however conveyed, or any document, print, tape, disk, semiconductor
memory or other information-conveying tangible article, unless Supplier has the
right to do so. Any information provided by Supplier which is confidential or
proprietary shall be provided in accordance with the Agreement Concerning
Disclosure of Information effective 9 September 1998.
ARTICLE 30 - TERMINATION
TSSL may at any time terminate this Agreement for its convenience, in whole or
in part, upon written notice to Supplier, for any reason whatsoever. In such
case, TSSL's liability shall be limited to Milestone Payments due as of the date
of termination and any additional amount due, whether engaged or incurred, for
work performed up to and including the date of termination (which amount shall
be substantiated with proof satisfactory to TSSL), and no further work will be
rendered by Supplier. Such payment shall constitute a full and complete
discharge of TSSL's obligations. In no event shall TSSL's liability exceed the
price set forth in this Agreement. Upon such a termination TSSL shall pay
Supplier moneys due and owing pursuant to this Article or Supplier shall refund
moneys due TSSL, if any.
ARTICLE 31- TOOLS AND EQUIPMENT
Unless otherwise specifically provided in this Agreement, Supplier shall provide
all labor, tools and equipment (the "tools") for performance of this Agreement.
ARTICLE 32 - USE OF INFORMATION
Any specifications, drawings, sketches, models, samples, tools, computer or
other apparatus programs, technical or business information or data, written,
oral or otherwise, owned or controlled by TSSL ("Information") furnished to or
acquired by Supplier under this Agreement of order, or in comtemplation of this
Agreement or order, shall remain TSSL's property. All copies of such
12 TSSL Proprietary
Contract Number 81163-PPCG
14 March 2000
Information in written, graphic or other tangible form shall be returned to TSSL
at its request. Unless such Information was previously known to Supplier free of
any obligation to keep it confidential, or has been or is subsequently made
public by TSSL or third party, it shall be kept confidential by Supplier, shall
be used only in the filling of orders or in performing under this Agreement or
order, and may not be used for other purposes except upon such terms as may be
agreed upon between Supplier and TSSL in writing.
ARTICLE 33 - WAIVER
The failure of either party at any tine to enforce any right or remedy available
to it under this Agreement or otherwise with respect to any breach or failure by
the other party shall not be construed to be a waiver of such right or remedy
with respect to any other breach or failure by the other party.
ARTICLE 34 - WARRANTY FOR PROTOTYPES AND PREPRODUCTION
Supplier warrants to TSSL and its customers that the Work furnished will be free
from defects in design (except to the intent designed by TSSL), material and
workmanship and will conform to and perform in accordance with the
specifications, drawings and samples. In addition, if the Work contains one or
more manufacturer's warranties, Supplier hereby assigns such warranties to TSSL
and its customers for the full duration thereof. All warranties shall survive
inspection, acceptance and payment. Work not meeting the warranties will be, at
TSSL's option, adjusted or replaced by Supplier (on an overtime basis, if
necessary, to avoid interference with plant operation), at no cost to TSSL and
its customers.
ARTICLE 35 - FORCE MAJEURE
Neither party shall be held responsible for any delay or failure in performance
of any part of this Agreement to the extent such delay or failure is caused by
fire, flood, explosion, war, strike, embargo, government requirement, civil or
military authority, act of God, or other similar causes beyond its control and
without the fault or negligence of the delayed or nonperforming party or its
subcontractors ("force majeure conditions"). Notwithstanding the foregoing,
Supplier's liability for loss or damage to TSSL's material in Supplier's
possession or control shall not be modified by this clause. If any force majeure
condition occurs, the party delayed or unable to perform shall give immediate
notice to the other party, stating the nature of the force majeure condition and
any action being taken to avoid or minimize its effect. The party affected by
the other's delay or inability to perform may elect to:
(1) suspend this Agreement or an order for the duration of the force majeure
condition and (i) at its option buy, sell, obtain or furnish elsewhere material
or services to be bought, sold, obtained or furnished under this Agreement or an
order (unless such sale or furnishing is prohibited under this Agreement) and
deduct from any commitment the quantity bought, sold, obtained or furnished or
for which commitments have been made elsewhere and (ii) once the force majeure
condition ceases, resume performance under this Agreement or an order with an
option in the affected party to extend the period of this Agreement or order up
to the length of time the force majeure condition endured and/or (2) when the
delay or nonperformance continues for a period of at least fifteen (15) days,
terminate, at no charge, this Agreement or an order or the part of it relating
to material not already shipped, or services not already performed. Unless
written notice is given within forty-five (45) days
TSSL Proprietary
13
Contract Number 81163-PPCG
14 March 2000
after the affected party is notified of the force majeure condition, (1) shall
be deemed selected.
ARTICLE 36 - COMPLIANCE WITH LAWS
Supplier and all persons furnished by Supplier shall comply at their own expense
with all applicable federal, state, local and foreign laws, ordinances,
regulations and codes, including those relating to the use of
chlorofluorocarbons, and including the identification and procurement of
required permits, certificates, licenses, insurance, approvals and inspections
in performance under this Agreement. Supplier agrees to indemnify, defend (at
TSSL's request) and save harmless TSSL, its affiliates, its and their customers
and each of their officers, directors and employees from and against any losses,
damages, claims, demands, suits, liabilities, fines, penalties and expenses
(including reasonable attorney's fees) that arise out of or result from failure
to do so.
ARTICLE 37 - CHOICE OF LAW
The construction, interpretation and performance of this Agreement and all
transactions under it shall be governed by the laws of the State of New Jersey
excluding its choice of law rules and excluding the Convention for the
International Sale of Goods. The parties agree that the provisions of the New
Jersey Uniform Commercial Code apply to this Agreement and all transactions
under it, including agreements and transactions relating to the furnishing of
services, the lease or rental of equipment or material, and the license of
software. Supplier agrees to submit to the jurisdiction of any court wherein an
action is commenced against TSSL based on a claim for which Supplier has agreed
to indemnify TSSL under this Agreement.
ARTICLE 38 - JURISDICTION
Supplier agrees that any action or legal proceeding arising out of this
Agreement shall be brought only in a court of competent jurisdiction in the
State of New Jersey, United States of America, and Supplier expressly submits
to, and accepts the jurisdiction of, any such court in connection with such
action or proceeding and Supplier further consents to the enforcement of any
judgement against Supplier arising therefrom in any jurisdiction in which it has
or shall have any assets.
ARTICLE 39 - SURVIVAL OF OBLIGATIONS
The obligations of the parties under this Agreement which by their nature would
continue beyond the termination, cancellation or expiration of this Agreement,
including, by way of illustration only and not limitation, those in the clauses
COMPLIANCE WITH LAWS, IDENTIFICATION, IMPLEADER, INDEMNITY, INFRINGEMENT,
INSURANCE, RELEASES VOID, USE OF INFORMATION and WARRANTY, shall survive
termination, cancellation or expiration of this Agreement.
14 TSSL Proprietary
Contract Number 81163-PPCG
14 March 2000
ARTICLE 40 - ENTIRE AGREEMENT
This Agreement shall incorporate the typed or written provisions on TSSL's
orders issued pursuant to this Agreement and shall constitute the entire
agreement between the parties with respect to the subject matter of this
Agreement and the order(s) and shall not be modified or rescinded, except by a
writing signed by Supplier and TSSL. All references in these terms and
conditions to this Agreement or to Work, services, material, equipment,
products, software or information furnished under, in performance of, pursuant
to, or in contemplation of, this Agreement shall also apply to any orders issued
pursuant to this Agreement. Printed provisions on the reverse side of TSSL's
orders (except as specified otherwise in this Agreement) and all provisions on
Supplier's forms shall be deemed deleted. Additional or different terms inserted
in this Agreement by Supplier, or deletions thereto, whether by alterations,
addenda, or otherwise, shall be of no force and effect, unless expressly
consented to by TSSL in writing. Estimates or forecasts furnished by TSSL shall
not constitute commitments. The provisions of this Agreement supersede all
contemporaneous oral agreements and all prior oral and written quotations,
communications, agreements and understandings of the parties with respect to the
subject matter of this Agreement. The term "Work" as used in this Agreement may
also be referred to as "services."
AGREED:
MULTILINK TECHNOLOGY CORP. TYCO SUBMARINE SYSTEMS LTD
Signature /s/ ▇▇▇▇▇▇▇ ▇. ▇▇▇▇▇▇▇▇▇▇ Signature /s/ ▇▇▇ ▇. ▇▇▇▇▇▇▇ III
---------------------------- ----------------------------
Name ▇▇▇▇▇▇▇ ▇. ▇▇▇▇▇▇▇▇▇▇ Name ▇▇▇ ▇. ▇▇▇▇▇▇▇ III
--------------------------------- ---------------------------------
Title President and CEO Title Contracts Manager
-------------------------------- --------------------------------
Date 4/28/00 Date May 2, 2000
--------------------------------- --------------------------------
15 TSSL Proprietary
EXHIBIT A
AGREEMENT -- [*]
DATED 26 January 2000
I. Development
The following items will be developed under and for this program, in compliance
with the specifications provided in Exhibit B:
A. Custom [*] with input data rates from [*]
(developed with Multilink-owned proprietary IC blocks)
B. Custom [*] with input data rates from [*]
(developed with Multilink-owned proprietary IC blocks)
C. Board assembly [*]
D. Board assembly [*]
E. Board assembly [*]
F. Board assembly [*]
II. Multilink Products
The following Multilink products may also be used in this project:
A. MTC1204A - 9.95Gb/s CDRDMux IC
B. MTC1207D - 12.25Gb/s 16:1 MuxCMU IC
C. MTC1207A - 9.95Gb/s 16:1 MuxCMU IC
D. MTC1206D - 12.25Gb/s 1:16 Demultiplexer IC
E. MTC1205D - 12.25Gb/s 16:1 Multiplexer IC (as alternate to item B if
needed)
F. MTC5585D - 12.25Gb/s Clock/Data Recovery
G. Active Splitter/Differentiator
H. Passive Splitter
I. Delay Line
J. Resonant limiting Amplifier
K. Dielectric Resonator Filter
L. Limiting Amplifier
M. 1:16 Digital DMUX
N. 16:128 Demux and 128:16 gate array cells and architectural blocks
Many of these products are currently under development by Multilink and may be
required for the TSSL development effort. The cost associated with the
development effort for these components is being funded and paid for by
Multilink.
III. Deliverables
Multilink shall provide the following design documentation for the [*] devices:
a) Final Technical Specifications
b) Block Diagram and Simultation
c) Schematic Design and Simultation
d) Chip Layout and Tape Out
e) Test Specification
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Multilink shall provide the following design documentation for each of the
boards
a) Final Technical Specification
b) Block Diagram and Schematic
c) Test Specifications
Multilink will deliver working Prototypes for each Board in accordance with the
Schedule. [*] initial Prototypes of each Board will be delivered based on the
milestone schedule in Exhibit C. An additional [*] total prototype board sets in
total, as requested by TSSL, will be provided throughout [*] on a weekly
delivery basis. Prototypes and Pre-production units may be provided on an as-is
basis and may not fully comply with the qualification and workmanship
requirements of production units. Agreement on the configuration of the
Prototypes and Pre-production units will be reached by the Parties prior to
shipment if the Prototypes and Pre-production units are not in compliance with
applicable Specifications, Exhibit B. Agreement on test and qualification
procedures will be negotiated by the Parties.
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
EXHIBIT B
SPECIFICATIONS
AGREEMENT [*]
SPECIFICATIONS:
1) Component Specification for [*] dated
[*]
2) Component Specification for [*] dated
[*]
3) Component Specification for [*] dated
[*]
4) Component Specification for [*] dated
[*]
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number ########
Component Specification for
TSSL Part Number #######
[*]
---------------------------------------
This document is TSSL Proprietary.
Use pursuant to Company Instructions and applicable
Non-Disclosure Agreements
Revision History
-----------------------------------------------------------------------------------------------------
Issue # Date Author Reason for Re-issue
-----------------------------------------------------------------------------------------------------
1 [*] [*] Initial Release
-----------------------------------------------------------------------------------------------------
2 [*] [*] Spec. negotiation
-----------------------------------------------------------------------------------------------------
3 [*] [*] Spec. negotiation
-----------------------------------------------------------------------------------------------------
4 [*] [*] Module drawing update
Specs for [*]
Update low speed logic levels
-----------------------------------------------------------------------------------------------------
5 [*] [*] Remove [*] input
Modified specs on low speed clock, data,
and alarm outputs
Moved sub-rate clock outputs from SMB
connectors to parallel connector
-----------------------------------------------------------------------------------------------------
6 [*] [*] Remove +8 (volts) supply, Add +5 (volts) supply.
Reduce run length tolerance to [*]
Change specs for (volts)th and (volts)ph
Change levels and impedance of low speed data.
Change levels and impedance of low speed clocks
Change impedance of alarm outputs
Change rise/fall times of low speed clocks
Change impedance of alarm outputs
Change CLK3 over/under shoot to 10%
Spec'd CLK3 output impedance
Spec'd temperature sensors
Removed LOS alarm
Spec'd connector type
Spec'd module thickness
-----------------------------------------------------------------------------------------------------
7 [*] [*] All changes in Red Bold
Removed specs in Black Bold Strikethrough
-----------------------------------------------------------------------------------------------------
TSSL PROPRIETARY
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7
1/17/2000 Sheet 1 of 166
Tyco Submarine Systems, Ltd Issue 7
TSSL Part Number ########
[*]
[*]
-------------------------------------------
1. General Description
1.1. This module accepts a [*] data stream and performs the following
functions
. Quantization of the input signal with user controllable decision
threshold
. Recovers the [*] clock
. Retimes the data with user controllable decision phase
. Demultiplexes the data [*] to [*] then [*] to [*] to produce a
parallel data word, one [*] , and [*] differential clocks
1.2. This module produces the following output signals:
. Quantized replica of input data at [*]
. Recovered [*] clock
. Demultiplexed [*] bit wide data word
. One [*] MHz differential sub-rate clock
. Two [*] MHz differential low speed clocks
. Alarm signal
2. Block Diagram and I/O Definitions
[*]
[*]
TSSL PROPRIETARY
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7
1/17/2000 Sheet 2 of 166
Tyco Submarine Systems, Ltd Issue 7
TSSL Part Number ########
[*]
--------------------------------------------------------------------------------
Table 1 - I/O Signal Descriptions
Signal Description
Din [*] input data signal
Vth Decision threshold adjustment
Vph Decision phase adjustment
Vcc1 DC power supply
Vcc2 DC power supply
Vee1 DC power supply
Vee2 DC power supply
Removed from specs
Cmon Recovered clock monitor
D\\coo\\ - D\\127\\ [*] Demultiplexed data
▇▇▇▇, ▇▇▇▇ Differential [*] clocks
CLK3 Differential [*] sub-rate clock
LOC Loss of clock alarm
--------------------------------------------------------------------------------
TSSL PROPRIETARY
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7
1/17/2000 Sheet 3 of 166
Tyco Submarine Systems, Ltd Issue /
[*] TSSL Part Number ########
3. Module Specifications
3.1. DC Power
------------------------------------------------------------------------------------------------------------------------------------
Table 2 - DC Power Specifications
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
------------------------------------------------------------------------------------------------------------------------------------
Power Dissipation Pdisp 11 W
------------------------------------------------------------------------------------------------------------------------------------
Supply Voltages (Volts)cc1 [*] [*] [*] (Volts) All power supplies:+/- 7% tolerance
(Volts)cc2 [*] [*] [*] (Volts)
(Volts)ee1 [*] [*] [*] (Volts)
(Volts)ee2 [*] [*] [*] (Volts)
------------------------------------------------------------------------------------------------------------------------------------
Current Draw lcc1 [*] meters(amps)
lcc2 [*] meters(amps)
lee1 [*] meters(amps)
lee2 [*] meters(amps)
------------------------------------------------------------------------------------------------------------------------------------
Power Supply Sequencing Module shall be insensitive to supply
power-up and power-down sequencing
or timing.
------------------------------------------------------------------------------------------------------------------------------------
Power Failure Tolerance Failure of one or more supplies will
not cause damage to module.
------------------------------------------------------------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY Sheet 4 of 166
1/17/2000
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number ########
3.2. High Speed Input Signal
------------------------------------------------------------------------------------------------------------------------------------
Table 3 - High Speed Input Specifications
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
------------------------------------------------------------------------------------------------------------------------------------
Input Data Rate [*] [*] [*] Gb/s
------------------------------------------------------------------------------------------------------------------------------------
Input Data Format NRZ
------------------------------------------------------------------------------------------------------------------------------------
Input Pattern Tolerance Module must work properly with a
101010...... Input pattern.
------------------------------------------------------------------------------------------------------------------------------------
Maximum Tolerable Run [*] All 1's or all 0's
Length
------------------------------------------------------------------------------------------------------------------------------------
Input Data Amplitude (volts)_Din [*] [*] [*] (metres)(volt)p-p
------------------------------------------------------------------------------------------------------------------------------------
Input Data Connector [*]
------------------------------------------------------------------------------------------------------------------------------------
Input Data Coupling [*]
------------------------------------------------------------------------------------------------------------------------------------
[*] [*]
------------------------------------------------------------------------------------------------------------------------------------
Input Low End Cutoff F_low_Din [*] [*] KHz 3 dB down
------------------------------------------------------------------------------------------------------------------------------------
Input Impedance Z_Din [*] ohm
------------------------------------------------------------------------------------------------------------------------------------
Input Return Loss S11_Din dB 150 MHz F 11 GHz
[*] (S11 greater than 10 dB down to
▇▇▇ ▇▇▇ ▇▇▇▇▇▇▇▇▇▇▇ by
qualification measurement)
------------------------------------------------------------------------------------------------------------------------------------
Input Return Loss S11_Din [*] dB 11 GHz less than F 16 GHz
Established by qualification
measurement
------------------------------------------------------------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPREITARY
1/17/2000 Sheet 5 of 166
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number ########
3.3. Control Inputs
------------------------------------------------------------------------------------------------------------------------------------
Table 4 - Control Input Specifications
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
------------------------------------------------------------------------------------------------------------------------------------
Decision Threshold % of input
Adjustment Range Capability [*] [*] eye amp.
------------------------------------------------------------------------------------------------------------------------------------
(volts)th for decision threshold at (Volts)th_min (Volts)
10% of eye amplitude [*] [*]
------------------------------------------------------------------------------------------------------------------------------------
(volts)th for decision threshold at (Volts)th_max (Volts)
90% of eye amplitude [*] [*]
------------------------------------------------------------------------------------------------------------------------------------
(volts)th_max-(volts)th_min [*] [*] (Volts) Assures adequately small
adjustment granularity
for digital control of
(Volts)th
------------------------------------------------------------------------------------------------------------------------------------
(Volts)th input resistance R_(Volts)th [*] K (ohm)
------------------------------------------------------------------------------------------------------------------------------------
(Volts)th High End Cutoff F_high_(Volts)th [*] kHz 3 dB down
------------------------------------------------------------------------------------------------------------------------------------
Decision Phase Adjustment [*] [*] ps Relative to center of
Range Capability eye Goal of + 25 ps
------------------------------------------------------------------------------------------------------------------------------------
(Volts)ph for decision phase at eye (Volts)ph_min (Volts)
center -20 ps [*]
------------------------------------------------------------------------------------------------------------------------------------
(Volts)ph for decision phase at eye (Volts)ph_max [*] (Volts)
center +20 ps
------------------------------------------------------------------------------------------------------------------------------------
(Volts)ph_max-(Volts)ph_min [*] [*] (Volts) Assures adequately small
adjustment granularity
for digital control of
(Volts)ph
------------------------------------------------------------------------------------------------------------------------------------
(Volts)ph monotonicity Absolutely monotonic
over (Volts)ph_min to
(Volts)ph_ max
------------------------------------------------------------------------------------------------------------------------------------
Instantaneous slope of Phase d(Phase) ps/100 Measured over range
-------- (metres) (Volts)ph_min to
vs (Volts)ph curve d(Voltsph) [*] Volts (Volts)ph_max
------------------------------------------------------------------------------------------------------------------------------------
(Volts)ph input resistance R_(Volts)ph [*] K (ohm)
------------------------------------------------------------------------------------------------------------------------------------
(Volts)ph High End Cutoff F_high_(Volts)ph [*] kHz 3 dB down
------------------------------------------------------------------------------------------------------------------------------------
Confidential matters omitted and filed separately with the securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/7/2000 Sheet 6 of 166
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number ########
3.4. Low Speed Outputs
------------------------------------------------------------------------------------------------------------------------------------
Table 5 - Low Speed Outputs
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
====================================================================================================================================
Data output rate [*] Mb/s (Input data rate) + 128
------------------------------------------------------------------------------------------------------------------------------------
Output clock frequency [*] MHz (Input data rate) + ▇▇▇
▇▇▇▇ ▇▇▇▇ ▇▇▇ ▇▇▇▇ are differential
clock outputs
------------------------------------------------------------------------------------------------------------------------------------
Short Circuit Tolerance All outputs shall be able to withstand an
infinite duration short to ground without
sustaining damage.
------------------------------------------------------------------------------------------------------------------------------------
Data logic HIGH level (volts)_data_(high) [*] [*] [*] (milli volts) CMOS drivers with 68 (ohm) output
Impedence
------------------------------------------------------------------------------------------------------------------------------------
Data logic LOW level (volts)_data_(low) [*] [*] (milli volts) CMOS drivers with 68 (ohm) output
Impedence
------------------------------------------------------------------------------------------------------------------------------------
Data transmission line (impedence)_data [*] (ohm) See data output driver equivalent circuit
impedance on module figure
------------------------------------------------------------------------------------------------------------------------------------
Cross talk [*] db data to data, data to clock, clock to data
------------------------------------------------------------------------------------------------------------------------------------
"Eye" cross position Eye_cross [*] [*] % of eye
------------------------------------------------------------------------------------------------------------------------------------
Clock - Data relationship Low speed data shall be clocked out of the
CDR/DEMUX module on the RISING edge of CLK1
------
------------------------------------------------------------------------------------------------------------------------------------
Clock output coupling [*] All low speed clock outputs
------------------------------------------------------------------------------------------------------------------------------------
Clock logic HIGH level (volts)_clk_(high) [*] [*] [*] (milli volts) CMOS drivers with 68 (ohm) output
Impedence
Amplitude defined to high impedance
load (open)
Each low speed clock output, single
ended, driving 50 (ohm) load
------------------------------------------------------------------------------------------------------------------------------------
Data logic LOW level (volts)_clk_(low) [*] [*] (milli volts) CMOS drivers with 68 (ohm) output impedance
Amplitude defined to high impedance load
(open)
Each low speed clock output, single ended,
driving 50 (ohm) load
------------------------------------------------------------------------------------------------------------------------------------
Clock transmission line (impedence)_clk [*] (ohm) All low speed clock outputs. See clock
impedence on module output driver equivalent circuit figure
------------------------------------------------------------------------------------------------------------------------------------
Data output rise / fall time (rise time)_data [*] [*] (nano seconds) 20 to 80%, see timimg diagram
(fall time)_data
------------------------------------------------------------------------------------------------------------------------------------
Clock output rise / fall time (rise time)_clk, [*] [*] (nano seconds) 20 to 80%, see timing diagram
(fall time)_clk
------------------------------------------------------------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/17/2000 Sheet 7 of 166
Tyco Submarine Systems, Ltd Issue 7
[*] SSL Part Number #########
-----------------------------------------------------------------------------------------------------------------------------------
Table 5 - Low Speed Outputs (continued)
----------------------------------------------------------------------------------------------------------------------------------
Output clock duty cycle Dcyc [*] [*] % All clock outputs
----------------------------------------------------------------------------------------------------------------------------------
CLK1 to CLK1_b and ▇▇▇▇ ▇▇▇▇_▇▇▇▇ [*] (nano seconds) See timing diagram
to CLK2_b differential clock
skew
----------------------------------------------------------------------------------------------------------------------------------
CLK1 to data delay Tcd [*] [*] (nano seconds) See timing Diagram
Measured across D\\oco\\ - D\\127\\.
over temperature and supply
voltage range.
----------------------------------------------------------------------------------------------------------------------------------
CLK1 to data skew variation Tcd(max) - See timing Diagram
Tcd(min) [*] (nano seconds) Measured across D\\oco\\ - D\\127\\.
over temperature and supply
voltage range.
----------------------------------------------------------------------------------------------------------------------------------
Clock over / under shoot Ovrsh_c95, % of clock Applies to ▇▇▇▇, ▇▇▇▇_▇,
Undrsh_c95 [*] amplitude Clk2, and Clk2_b
----------------------------------------------------------------------------------------------------------------------------------
3.5. Alarms
-----------------------------------------------------------------------------------------------------------------------------------
Table 6 - Alarm Outputs
-----------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
===================================================================================================================================
LOC logic HIGH level Volts_LOC_High [*] [*] [*] (millivolts) Standard CMOS output
-----------------------------------------------------------------------------------------------------------------------------------
LOC logic LOW level Volts_LOC_Low [*] [*] (millivolts) Standard CMOS output
-----------------------------------------------------------------------------------------------------------------------------------
Short Circuit Tolerance All outputs shall be able
to withstand an Infinite
duration short to ground
without sustaining damage.
-----------------------------------------------------------------------------------------------------------------------------------
Removed from specs
-----------------------------------------------------------------------------------------------------------------------------------
LOC activate threshold Activated on input LOS
"noise" only input, and
input bit rate * 100 Mb/s
from nominal
Must distinguish between:
Vin valid signal and maximum
Vin wideband noise signal.
Must not generate the false
alarms
-----------------------------------------------------------------------------------------------------------------------------------
LOC activate / disable time T_LOC [*] (microseconds) Alarms are active HIGH
-----------------------------------------------------------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
* greater than
Issue 7 TSSL PROPRIETARY
1/17/2000 Sheet 8 of 166
Tyco Submarine Systems, Ltd Issue 7
[*] SSL Part Number #########
3.6. Monitor Outputs
-----------------------------------------------------------------------------------------------------------------------------------
Table 7 Monitor Port Specifications
-----------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
-----------------------------------------------------------------------------------------------------------------------------------
CMON and DMON connector [*]
-----------------------------------------------------------------------------------------------------------------------------------
CMON and DMON coupling [*]
-----------------------------------------------------------------------------------------------------------------------------------
Short Circuit Tolerance All outputs shall be able to
withstand an infinite
duration short to ground
without sustaining damage.
-----------------------------------------------------------------------------------------------------------------------------------
CMON output amplitude (Volts)_CMON [*] mVp-p
-----------------------------------------------------------------------------------------------------------------------------------
Removed from specs
-----------------------------------------------------------------------------------------------------------------------------------
Monitor output rise / fall times (risetime)_CMON ps
(falltime)_DMON
-----------------------------------------------------------------------------------------------------------------------------------
CMON and output [*] (ohms)
impedance
-----------------------------------------------------------------------------------------------------------------------------------
Required termination Termination insensitive
-----------------------------------------------------------------------------------------------------------------------------------
Removed from specs
-----------------------------------------------------------------------------------------------------------------------------------
Removed from specs
-----------------------------------------------------------------------------------------------------------------------------------
Removed from specs
-----------------------------------------------------------------------------------------------------------------------------------
CMON return loss s22_CMON [*] dB 12.0 * F 12.5 GHz.
-----------------------------------------------------------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
* less than
Issue 7 TSSL PROPRIETARY
1/17/2000 Sheet 9 of 166
Issue 7
Tyco Submarine Systems, Ltd TSSL Part Number ########
[*]
3.7. Sub-Rate Clock Outputs
-------------------------------------------------------------------------------------------------------------------------------
Table 8 - Sub-Rate Clock Outputs
-------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
===============================================================================================================================
Frequency [*] MHz (Input data rate) + 16
-------------------------------------------------------------------------------------------------------------------------------
Output Coupling [*]
-------------------------------------------------------------------------------------------------------------------------------
Short Circuit Tolerance All outputs shall be able to withstand an
infinite duration short to ground without
sustaining damage.
-------------------------------------------------------------------------------------------------------------------------------
Output Level (volts)_c622_diff [*] [*] (millivolt)p-p Differential, 400 mVp-p single ended
-------------------------------------------------------------------------------------------------------------------------------
Clock rise / fall time (Rise time)_c767 / [*] [*] [*] ps 20-80%
(fall time)_c767
-------------------------------------------------------------------------------------------------------------------------------
Clock duty cycle Dcyc [*] [*] % All clock outputs
-------------------------------------------------------------------------------------------------------------------------------
CLK3 to CLK3_b differential Tc767_skew [*] ps
clock skew
-------------------------------------------------------------------------------------------------------------------------------
Clock over / under shoot Ovrsh_c767 % of clock Applies to CPx3 and Clk3_b
Undrsh_c767 [*] amplitude
-------------------------------------------------------------------------------------------------------------------------------
Clock output impedance (impedence)_c767 [*] OHM Applies to Clk3 and Clk 3_b
-------------------------------------------------------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/17/2000 Sheet 10 of 166
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number ########
3.8. Jitter Performance
-----------------------------------------------------------------------------------------------------------------------
Table 9 - Jitter Specifications
-----------------------------------------------------------------------------------------------------------------------
Parameter Symbol * Min Typ Max Units Comments
=======================================================================================================================
Jitter Tolerance JTOL [*]
-----------------------------------------------------------------------------------------------------------------------
Jitter Transfer Function JTF [*] dB DC to 10 KHz
-----------------------------------------------------------------------------------------------------------------------
Jitter Generation JGEN [*] Ulp-p 50 to KHz 80 MHz
-----------------------------------------------------------------------------------------------------------------------
3.9. Temperature Sensors
-----------------------------------------------------------------------------------------------------------------------
Table 10 - Temperature Sensor Outputs
-----------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
=======================================================================================================================
12G Demux sensor: 2(Volts)be - type sensor in GaAs
Parameters:
a) Volts/Time TBD
b) (current)Fmax TBD
-----------------------------------------------------------------------------------------------------------------------
Low Speed Demux sensor [*] Sink current output
-----------------------------------------------------------------------------------------------------------------------
3.10 Miscellaneous
-----------------------------------------------------------------------------------------------------------------------
Table 11 - Miscellaneous Specifications
-----------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
=======================================================================================================================
Lifetime [*] Years
-----------------------------------------------------------------------------------------------------------------------
Failure Rate [*] FIT FIT = Failures in 10/?/ hours
-----------------------------------------------------------------------------------------------------------------------
Environmental Requirements [*] Supplied by TSSL. Exceptions granted
on case by case basis.
-----------------------------------------------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/17/2000 Sheet 11 of 166
Issue 7
Tyco Submarine Systems, Ltd TSSL Part Number ########
[*]
3.11. Timing Diagrams
[*]
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
TSSL PROPRIETARY
Issue 7 Sheet 12 of 166
1/17/2000
Issue 7
Tyco Submarine Systems, Ltd TSSL Part Number ########
[*]
3.12. Output Driver Equivalent Circuits
3.13. Output Driver Equivalent Circuits
[*]
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
TSSL PROPRIETARY
Issue 7 Sheet 13 of 166
1/17/2000
Issue 7
Tyco Submarine Systems, Ltd [*] TSSL Part Number ########
[*]
4. Mechanical Requirements
4.1. Module I/O Placement
The sub-rate clocks and all low speed signals (data, clock, control,
power) shall be connected to the module through [*]
[*] ). Figure 4 shows a rough diagram of the module I/O layout. For
exact details, see the appropriate mechanical drawing.
[*]
[*]
Confidential materials omitted and filed separately with the Securities and
Exchange commission. Asterisks denote omissions.
TSSL PROPRIETARY
Issue 7 Sheet 14 of 166
1/17/2000
Issue 7
Tyco Submarine Systems, Ltd TSSL Part Number ########
[*]
4.2. Output Bit Ordering
The order of the bits at the [*] outputs is affected by the fact [*]
[*] Assuming that the input bit order is:
[*]
The de-multiplexed bits shall appear at the module's low speed output
connector in the order shown in Table 10.
The layout of the module's IC's, substrate and connector shall be such that
[*]
[*]
[*]
Table 10 - Output Bit Ordering
-------
D127
-------
D111
-------
D095
-------
D079
-------
D063
-------
D047
-------
D031
-------
D015
-------
----
-------
D014
-------
----
-------
D013
-------
----
-------
D012
-------
----
-------
D011
-------
----
-------
DO10
-------
----
-------
D009
-------
----
-------
D008
-------
----
-------
D007
-------
----
-------
D006
-------
----
-------
D005
-------
----
-------
D004
-------
----
-------
D003
-------
----
-------
D002
-------
D113
-------
D097
-------
D081
-------
D065
-------
D049
-------
D033
-------
D017
-------
D001
-------
D112
-------
D096
-------
D080
-------
D064
-------
D048
-------
D032
-------
D016
-------
D000
-------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
TSSL PROPRIETARY
Issue 7 Sheet 15 of 166
1/17/2000
Issue 7
Tyco Submarine Systems, Ltd TSSL Part Number ########
[*]
4.3. Thermal Management
The primary heat removal method shall be conduction through the
module's base plate (non-component side) that will be attached to an
appropriate heat sink.
4.4. Product Marking
TBD
---
5. Product Documentation
5.1. Test Results
TBD
---
5.2. Warranty Information
TBD
---
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
TSSL PROPRIETARY
Issue 7 Sheet 16 of 166
1/17/2000
Issue 7
Tyco Submarine Systems, Ltd TSSL Part Number ########
[*]
=Component Specification for
TSSL Part Number #######
[*]
____________________________________
This document is TSSL Proprietary.
Use pursuant to Company Instructions and applicable
Non-Disclosure Agreements
Revision History
--------------------------------------------------------------------------------
Issue # Date Author Reason for Re-issue
--------------------------------------------------------------------------------
1 [*] [*] Initial Release
--------------------------------------------------------------------------------
2 [*] [*] Spec. negotiation
--------------------------------------------------------------------------------
3 [*] [*] Spec. negotiation
--------------------------------------------------------------------------------
4 [*] [*] Module drawing updated
Specs for (volts)gain
Updated low speed logic levels
--------------------------------------------------------------------------------
5 [*] [*] Modified specs on low speed clock, data, and
alarm outputs
Moved sub-rate clock outputs from SMB
connectors to parallel connector
Removed (volts)gain
--------------------------------------------------------------------------------
6 [*] [*] Added +5 (volts) supply.
Reduced run length tolerance to [*]
Changed levels & impedance of low speed data
Changed levels & impedance of low speed clocks
Changed impedance of alarm outputs
Changed rise/fall times of low speed clocks
Changed impedance of alarm outputs
Changed CLK3 over/under shoot to 10%
Spec'd CLK3 output impedance
Spec'd temperature sensors
Removed LOC
Spec'd connector type
Spec'd module thickness
--------------------------------------------------------------------------------
7 [*] [*] Changes in Bold Red
--------------------------------------------------------------------------------
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Exchange Commission. Asterisks denote omissions.
TSSL PROPRIETARY
Issue 7 Sheet 1 of 16
1/17/2000
Tyco Submarine Systems, Ltd Issue 7
TSSL Part Number ########
[*]
--------------------------------------------------------------------------------
[*] Removed Specs in Bold Black Striketrough
--------------------------------------------------------------------------------
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Issue 7 Sheet 2 of 16
1/17/2000
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number #######
[*]
----------------------------------------------
1. General Description
1.1. This module accepts a [*] data stream and performs the following
functions
. Recovers the [*] clock
. Quantizes and retimes input data with the recovered clock
optimally phase aligned in data eye
. Demultiplexes the data [*] to produce a parallel data word,
[*] , and [*] differential clocks
1.2. The module produces the following output signals:
. [*] data word
. [*] low speed clocks
. [*] sub-rate clock
. LOS Alarm signal
2. Block Diagram and I/O Definitions
[*]
[*]
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Issue 7 Sheet 3 of 16
1/17/2000
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number #######
[*]
----------------------------------------------
------------------------------------------------------------------------------
Table 1-I/0 Signal Descriptions
Signal Description
Din [*] input data signal
(Volts)cc1 DC power supply
(Volts)cc2 DC power supply
(Volts)ee1 DC power supply
Removed from specs
D\\000\\ - D\\127\\ [*] Demultiplexed data
▇▇▇▇, ▇▇▇▇ Differential [*] clocks
CLK3 Differential [*] sub-rate clock
LOS Loss of signal alarm
(Volts)th Decisions threshold adjustment
------------------------------------------------------------------------------
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Issue 7 Sheet 4 of 16
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Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number ########
3. Module Specifications
3.3. DC Power
----------------------------------------------------------------------------------------------------------------
Table 2 - DC Power Specifications
----------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
----------------------------------------------------------------------------------------------------------------
Power Dissipation Pdisp [*] W Design Goal: 8 W max
----------------------------------------------------------------------------------------------------------------
Supply Voltages (volts)cc1 [*] [*] [*] (volts) Power supplies tolerance
(volts)cc2 [*] [*] [*] (volts) +7%
(volts)ee1 [*] [*] [*] (volts)
[*] (volts)
----------------------------------------------------------------------------------------------------------------
Current Draw lcc1 [*] (meters)(amp)
lcc2 [*] (meters)(amp)
lee1 [*] (meters)(amp)
[*]
----------------------------------------------------------------------------------------------------------------
Power Supply Sequencing Module shall be insensitive
to supply power-up and
power-down sequencing
or timing.
----------------------------------------------------------------------------------------------------------------
Power Failure Tolerance Failure of one or more
supplies will not cause
damage to module.
----------------------------------------------------------------------------------------------------------------
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1/17/2000 Sheet 5 of 16
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number #########
3.4. High Speed Input Signal
------------------------------------------------------------------------------------------------------------------------------------
Table 3 - High Speed Input Specifications
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
====================================================================================================================================
Input Data Rate [*] [*] [*] Gb/s OC-192 / STM-64 Rate
------------------------------------------------------------------------------------------------------------------------------------
Input Data Format NRZ
------------------------------------------------------------------------------------------------------------------------------------
Input Pattern Tolerance Module must work properly
with a 101010.....input
pattern.
------------------------------------------------------------------------------------------------------------------------------------
Maximum Tolerable Run All 1's or all 0's
Length [*]
------------------------------------------------------------------------------------------------------------------------------------
Input Data Amplitude (Volts)_Din [*] [*] [*] (millivolts)p-p
------------------------------------------------------------------------------------------------------------------------------------
Input Data Connector
[*]
------------------------------------------------------------------------------------------------------------------------------------
Input Data Coupling [*]
------------------------------------------------------------------------------------------------------------------------------------
Input High End Cutoff F_high_Din [*] GHz 3 dB down
------------------------------------------------------------------------------------------------------------------------------------
Input Low End Cutoff F_low_Din [*] KHz 3 dB down
------------------------------------------------------------------------------------------------------------------------------------
Input Impedance (impedence)_Din [*] [ohm]
------------------------------------------------------------------------------------------------------------------------------------
Input Return Loss S11_Din [*] dB 50 MHz F 8.0 GHz
(S11 ** 10 dB down to 150
KHz established by
qualification measurement)
------------------------------------------------------------------------------------------------------------------------------------
** greater than
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1/17/2000 Sheet 6 of 16
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[*] TSSL Part Number ########
3.5 High Speed Input Signal
------------------------------------------------------------------------------------------------------------------------------------
Table 4 - Control Input Specifications
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
====================================================================================================================================
Decision Threshold [*] [*] % of input
Adjustment Range Capability eye amp.
------------------------------------------------------------------------------------------------------------------------------------
Vth for decision threshold at Vth_min [*] [*] (Volts)
10% of eye amplitude
------------------------------------------------------------------------------------------------------------------------------------
Vth for decision threshold at Vth_max [*] [*] [*] (Volts)
90% of eye amplitude
------------------------------------------------------------------------------------------------------------------------------------
Vth_max-Vth_min [*] [*] (Volts) Assures adequately small
adjustment granularity for
digital control of Vth
------------------------------------------------------------------------------------------------------------------------------------
Vth input resistance R_Vth [*] (Kido)(ohm)
------------------------------------------------------------------------------------------------------------------------------------
Vth High End Cutoff F_high_Vth [*] kHz 3 dB down
------------------------------------------------------------------------------------------------------------------------------------
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1/17/2000 Sheet 7 of 16
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[*] TSSL Part Number ########
3.6. Low Speed Outputs
------------------------------------------------------------------------------------------------------------------------------------
Table 5 - Low Speed Outputs
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
====================================================================================================================================
Data output rate [*] Mb/s (Input data rate) / 128
------------------------------------------------------------------------------------------------------------------------------------
Output clock frequency [*] MHz (Input data rate) / 128
Both CLK1 and CLK2 are
differential clock outputs
------------------------------------------------------------------------------------------------------------------------------------
Short Circuit Tolerance All outputs shall be able to
withstand an infinite duration
short to ground without sustaining
damage.
------------------------------------------------------------------------------------------------------------------------------------
Data logic HIGH level (Volts)_data_(High) CMOS drivers with 68 (ohm) output
[*] [*] [*] millivolts impedance
------------------------------------------------------------------------------------------------------------------------------------
Data logic LOW level (Volts)_data_(Low) CMOS drivers with 68 (ohm) output
[*] [*] millivolts impedance
------------------------------------------------------------------------------------------------------------------------------------
Data transmission line (impedence)_data See data output driver equivalent
impedance on module [*] (ohm) circuit figure
------------------------------------------------------------------------------------------------------------------------------------
Cross talk [*] dB data to data, data to clock,
clock to data
------------------------------------------------------------------------------------------------------------------------------------
"Eye" cross position Eye_cross [*] [*] % of eye
------------------------------------------------------------------------------------------------------------------------------------
Clock - Data relationship Low speed shall be clocked out
of the CDR/DEMUX module on the
RISING edge of CLK1
------
------------------------------------------------------------------------------------------------------------------------------------
Clock output coupling [*] All low speed clock outputs
------------------------------------------------------------------------------------------------------------------------------------
Clock logic HIGH level (Volts)_clk_(High) millivolts CMOS drivers with 68 (ohm) output
[*] [*] [*] impedance
Amplitude defined to high Impedance
load (open)
ended, driving 50 (ohm) load
------------------------------------------------------------------------------------------------------------------------------------
Data logic LOW level (Volts)_clk_(Low) [*] [*] millivolts CMOS drivers with 68 (ohm) output
impedance
Amplitude defined to high Impedance
load (open)
Each low speed clock output, single
ended, driving 50 (ohm) load
------------------------------------------------------------------------------------------------------------------------------------
Clock transmission line (impedence)_clk (ohm) All low speed clock outputs. See
impedance on module [*] clock output driver equivalent
circuit figure
------------------------------------------------------------------------------------------------------------------------------------
Data output rise / fall time (rise time)_data, (nano seconds) 20 to 80%, see timing diagram
(fall time)_data [*] [*]
-----------------------------------------------------------------------------------------------------------------------------------
Clock output rise / fall time (rise time)_clk, (fall time)_clk [*] [*] (nano seconds) 20 to 80%, see timing diagram
------------------------------------------------------------------------------------------------------------------------------
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TSSL PROPRIETARY
Issue 7 Sheet 8 of 16
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[*] TSSL Part Number ########
-----------------------------------------------------------------------------------------------------------------------------------
Table 5 - Low Speed Outputs (continued)
-----------------------------------------------------------------------------------------------------------------------------------
Output clock duty cycle Dcyc [*] [*] % All clock outputs
-----------------------------------------------------------------------------------------------------------------------------------
CLK1 to CLK1_b and ▇▇▇▇ ▇▇▇▇_▇▇▇▇ [*] (nano seconds) See timing diagram
to CLK2_b differential clock
skew
-----------------------------------------------------------------------------------------------------------------------------------
CLK1 to data delay Tcd [*] [*] (nano seconds) See timing diagram
Measured across Doco-D127.
Worst case over temperature
and supply voltage range.
-----------------------------------------------------------------------------------------------------------------------------------
CLK1 to date skew variation Tcd(max)- (nano seconds) See timing Diagram
Tcd(min) [*] Measured across Doco-D127.
Worst case over temperature
and supply voltage range.
-----------------------------------------------------------------------------------------------------------------------------------
Clock over / under shoot Ovrsh_c77, [*] % of clock Applies to ▇▇▇▇, ▇▇▇▇_▇, Clk2,
Undrsh_c77 amplitude and Clk2_b
-----------------------------------------------------------------------------------------------------------------------------------
3.7 Alarm Output
-----------------------------------------------------------------------------------------------------------------------------------
Table 6 - Alarm Output Specifications
-----------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
===================================================================================================================================
LOS logic High level (Volts)_LOS_H [*] [*] [*] (milli volts) Open collector. On-board Pull-up
Resistor of 10k(ohm)
-----------------------------------------------------------------------------------------------------------------------------------
LOS logic Low level (Volts)_LOS_L [*] [*] (milli volts)
-----------------------------------------------------------------------------------------------------------------------------------
Short Circuit Tolerance All outputs shall be able to
withstand an Infinite duration
short to ground without sustaining
damage
------------------------------------------------------------------------------------------------------------------------------------
See LOS output driver equivalent
Removal from specs circuit figure
------------------------------------------------------------------------------------------------------------------------------------
Din LOS activate threshold LOS_active [*]
------------------------------------------------------------------------------------------------------------------------------------
Din LOS hysteresis LOS_hyst [*]
------------------------------------------------------------------------------------------------------------------------------------
LOS activate / disable time T_LOS [*] [*] (micro seconds) Alarm is active HIGH
------------------------------------------------------------------------------------------------------------------------------------
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Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number ########
3.8. Sub-Rate Clock Outputs
------------------------------------------------------------------------------------------------------------------------------------
Table 7 - Sub-Rate Clock Outputs
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
====================================================================================================================================
Frequency [*] MHz (Input data rate) + 16
------------------------------------------------------------------------------------------------------------------------------------
Output Coupling [*]
------------------------------------------------------------------------------------------------------------------------------------
Short Circuit Tolerance All outputs shall be able to withstand an
infinite duration short to ground without
sustaining damage.
------------------------------------------------------------------------------------------------------------------------------------
Output Level (volts)_c622_diff [*] [*] (millivolts) Differential, 300 millivoltsp-p single ended
------------------------------------------------------------------------------------------------------------------------------------
Clock rise / fall time (rise time)_c622/ [*] [*] ps 20 - 80%
(fall time)_c622
------------------------------------------------------------------------------------------------------------------------------------
Clock duty cycle Dcyc [*] [*] % All clock outputs
------------------------------------------------------------------------------------------------------------------------------------
CLK3 to CLK3_b differential Tc622_skew [*] ps
clock skew
------------------------------------------------------------------------------------------------------------------------------------
Clock over / under shoot Ovrsh_c622, [*] % of clock Applies to Clk3 and Clk3_b
Undrsh_c622 amplitude
------------------------------------------------------------------------------------------------------------------------------------
Clock output impedance (impedence)_c767 [*] (ohm) Applies to Clk3 and Clk3_b
------------------------------------------------------------------------------------------------------------------------------------
3.9. Jitter Performance
------------------------------------------------------------------------------------------------------------------------------------
Table 8 - Jitter Specifications
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
====================================================================================================================================
Jitter Tolerance JTOL [*]
------------------------------------------------------------------------------------------------------------------------------------
Jitter Transfer Function JTF [*] dB DC to 10 KHz
(established by qualification measurement)
------------------------------------------------------------------------------------------------------------------------------------
Jitter Generation JGEN [*] Ulp-p 50 KHz - 80 MHz
------------------------------------------------------------------------------------------------------------------------------------
Issue 7 TSSL PROPRIETARY
1/17/2000 Sheet 10 of 16
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Tyco Submarine Systems, Ltd Issue7
[*] TSSL Part Number ########
3.10. Temperature Sensors
---------------------------------------------------------------------------------------------------------
Table 9 - Temperature Sensor Specifications
---------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
---------------------------------------------------------------------------------------------------------
10G Demux sensor: 2 Volts \\BE\\ -type sensor in GaAs
Parameters:
a) Volt/Time TBD
b) (current) \\ F\\max TBD
---------------------------------------------------------------------------------------------------------
Low Speed Demux sensor [*] Sink current output
---------------------------------------------------------------------------------------------------------
3.11. Miscellaneous
---------------------------------------------------------------------------------------------------------
Table 10 - Miscellaneous Specifications
---------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
---------------------------------------------------------------------------------------------------------
Lifetime [*] Years
---------------------------------------------------------------------------------------------------------
Failure Rate [*] FIT FIT = Failures in 10/9/ hours
---------------------------------------------------------------------------------------------------------
Environmental Requirements Supplied by TSSL. Exceptions
[*] granted on case by case basis.
---------------------------------------------------------------------------------------------------------
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Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/17/2000 Sheet 11 of 16
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number ########
3.12 Timing Diagrams
[*]
[*]
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Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/17/2000 Sheet 12 of 16
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number ########
3.13. Output Driver Equivalent Circuits
[*]
[*]
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Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/17/2000 Sheet 13 of 16
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number ########
4. Mechanical Requirements
4.14. Module I/O Placement
The sub-rate clocks and all low speed signals (data, clock, control,
power) shall be connected to the [*] through [*]
impedance controlled). Figure 4 shows a rough diagram of the module I/O
layout. For exact details, see the appropriate mechanical drawing.
[*]
[*]
[*]
Confidential materials omitted and filed separately with the Securities and
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Issue 7 TSSL PROPRIETARY
1/17/2000 Sheet 14 of 16
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number ########
4.15. Output Bit Ordering
The order of the bits at the [*] outputs is affected by the fact that [*]
[*] .Assuming that the input bit order is:
[*]
The de-multiplexed bits shall appear at the module's low speed output connector
in the order shown in Table 10. The layout of the module's IC's, substrate and
connector shall be such that all of the low speed data signals are located as
shown in figure 4. This assures that
[*] [*]
Table 10- Output Bit Ordering
---------
D127
---------
D111
---------
D095
---------
D079
---------
D063
---------
D047
---------
D031
---------
D015
---------
----
---------
D014
---------
----
---------
D013
---------
----
---------
D012
---------
----
---------
D011
---------
----
---------
D010
---------
----
---------
D009
---------
----
---------
D008
---------
----
---------
D007
---------
----
---------
D006
---------
----
---------
D005
---------
----
---------
D004
---------
----
---------
D003
---------
----
---------
D002
---------
D113
---------
D097
---------
D081
---------
D065
---------
D049
---------
D033
---------
D017
---------
D001
---------
D112
---------
D096
---------
D080
---------
D064
---------
D048
---------
D032
---------
D016
---------
D000
---------
Confidential materials omitted and filed separately with the Securities and
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Issue 7 TSSL PROPRIETARY
1/17/2000 Sheet 15 of 16
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number ########
4.16. Thermal Management
The primary heat removal method shall be conduction through the
module's base plate (non-component side) that will be attached to an
appropriate heat sink.
4.17. Product Marking
TBD
---
5. Product Documentation
5.18. Test Results
TBD
---
5.19. Warranty Information
TBD
---
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/17/2000 Sheet 16 of 16
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
Component Specification for
TSSL Part Number [*]
[*]
___________________________
This document is TSSL Proprietary
Use pursuant to Company Instructions and applicable
Non-Disclosure Agreements
Revision History
-------------------------------------------------------------------------------
Issue # Date Author Reason for Re-issue
---------------------------------------------------------------------------------
1 [*] [*] Initial Release
---------------------------------------------------------------------------------
2 [*] [*] Spec. negotiation
---------------------------------------------------------------------------------
3 [*] [*] Spec. negotiation
---------------------------------------------------------------------------------
4 [*] [*] Module drawing update
Block diagram labeling
Vterm bypass
----------------------------------------------------------------------------------
5 [*] [*] Removed Clk2
Changed high speed data output to DC coupling
Modified specs on alarm outputs
Moved sub-rate clock outputs from SMB
connectors to parallel connector
----------------------------------------------------------------------------------
6 [*] [*] Add +5 V supply
Change levels and impedance of low speed data.
Change levels and impedance of low speed clocks
Added rise/fall time for input low speed signals
Change CLK3 over/under shoot to 10%
Spec'd CLK3 output impedance
Spec'd temperature sensors
Spec'd connector type
Spec'd module thickness
----------------------------------------------------------------------------------
7 [*] [*] Removed Data_b output
Added LOC3 alarm
Updated supply voltages and currents
Changed levels of sub-rate clock outputs.
General clean up.
----------------------------------------------------------------------------------
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Exchange Commission. Asterisks denote omissions.
TSSL PROPRIETARY
Issue 7 Sheet 1 of 15
1/19/2000
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
[*]
-----------------------
1. General Description.
1.1. This module accepts [*]
differential clock at [*] . It performs the following functions:
. Uses the input clock as a reference to synthesize a [*] clock
. Multiplexes the input data [*] to produce [*]
[*]
. Uses the [*] clock as a reference to synthesize a [*] clock
. Multiplexes the internal rails [*] to produce a [*]
1.2. The module produces the following output signals:
. [*] output signal
. [*] output clock
. [*] differential sub-rate clock
. [*] alarm signals
2. Block Diagrams and I/O Definitions
[*]
[*]
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Exchange Commission. Asterisks denote omissions.
TSSL PROPRIETARY
Issue 7 Sheet 2 of 15
1/19/2000
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
--------------------------------------------------------------------------------
Table 1 - I/O Signal Descriptions
Signal Description
D\\000\\-- D\\127\\ [*] input data
Vth_data Input data threshold adjustment
Clk_in, Clk_in_b Differential [*] input clock
Vcc1 DC power supply
Vcc2 DC power supply
Vee1 DC power supply
Vee2 DC power supply
Data Differential [*] output signal
Clk1 [*] output clock
▇▇▇▇, ▇▇▇▇_▇ Differential [*] sub-rate clock
LOC1 Loss of input reference clock alarm-active high
LOC2 Loss of [*] VCO output alarm-active high
LOC3 Loss of PLL lock in [*] alarm-active high
Vterm_clk Clock signal termination voltage
--------------------------------------------------------------------------------
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Exchange Commission. Asterisks denote omissions.
TSSL PROPRIETARY
Issue 7 Sheet 3 of 15
1/19/2000
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3. Module Specifications
3.1. DC Power
------------------------------------------------------------------------------------------------------------------------------------
Table 2 - DC Power Specifications
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
------------------------------------------------------------------------------------------------------------------------------------
Power Dissipation Pdisp 10 (▇▇▇▇▇)
------------------------------------------------------------------------------------------------------------------------------------
Supply Voltages Vcc1 [*] [*] [*] (Volts) +7%
-
Vcc2 [*] [*] [*] (Volts) +7%
-
Vee1 [*] [*] [*] (Volts) +7%
-
Vee2 [*] [*] [*] (Volts) +5%
-
------------------------------------------------------------------------------------------------------------------------------------
Current Draw Icc1 [*] (Milli amps)
Icc2 [*] (Milli amps)
Iee1 [*] (Milli amps)
Iee2 [*] (Milli amps)
------------------------------------------------------------------------------------------------------------------------------------
Power Supply Sequencing Module shall be insensitive
to supply power-up and
power-down sequencing or
timing.
------------------------------------------------------------------------------------------------------------------------------------
Power Failure Tolerance Failure of one or more
supplies will not cause
damage to module.
------------------------------------------------------------------------------------------------------------------------------------
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Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 4 of 15
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3.2. Data Inputs
-----------------------------------------------------------------------------------------------------------------------------------
Table 3 - Data Receiver Specifications
-----------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
===================================================================================================================================
Input data rate [*] [*] [*] Mb/s 128 Parallel channels
-----------------------------------------------------------------------------------------------------------------------------------
Input impedance (impedence)_data [*] (ohm) Both to ground and (volts)
-----------------------------------------------------------------------------------------------------------------------------------
Input decision threshold (volts)_data [*] [*] (millivolts) Set by (volts) input
-----------------------------------------------------------------------------------------------------------------------------------
Vth input impedance (impedence)_Vth [*] (ohm) Both to ground and data inputs
-----------------------------------------------------------------------------------------------------------------------------------
Vth high end cutoff F_high_Vth [*] Hz 3 dB down
-----------------------------------------------------------------------------------------------------------------------------------
Data input logic LOW (volts)_data_low [*] (millivolts)
threshold
-----------------------------------------------------------------------------------------------------------------------------------
Data input logic HIGH (volts)_data_high [*] (millivolts)
threshold
-----------------------------------------------------------------------------------------------------------------------------------
Input data levels [*] [*] (millivolts) Each input to ground
-----------------------------------------------------------------------------------------------------------------------------------
Input data rise/fall times (rise time)_data (nanoseconds)
(fall time)_data [*]
-----------------------------------------------------------------------------------------------------------------------------------
Data transmission line (impedence)_data [*] (volts)
impedance on module
-----------------------------------------------------------------------------------------------------------------------------------
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Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 5 of 15
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3.3. Clock Inputs
------------------------------------------------------------------------------------------------------------------------------------
Table 4 - Clock Receiver Specifications
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
====================================================================================================================================
Input clock rate [*] [*] [*] MHz
------------------------------------------------------------------------------------------------------------------------------------
Input impedance (impedence)_clk [*] (ohm) Each input measured to
Vterm_clk
------------------------------------------------------------------------------------------------------------------------------------
Differential Input impedance (impedence)_clk_diff [*] (Kilo ohm) Between differential
inputs
------------------------------------------------------------------------------------------------------------------------------------
Clock HIGH level ("PECL") (Volts)_clk_H [*] [*] (milli volts) Each input to ground
------------------------------------------------------------------------------------------------------------------------------------
Clock LOW level ("PECL") (Volts(_clk_L [*] [*] (milli volts) Each input to ground
------------------------------------------------------------------------------------------------------------------------------------
Input clock over / under shoot [*] (percent)
------------------------------------------------------------------------------------------------------------------------------------
Clock termination voltage (Volts)term_clk [*] [*] [*] (milli volts) Generated off-module
and applied to Vterm-
clk input
------------------------------------------------------------------------------------------------------------------------------------
Input clock rise/fall times (risetime)_clk, (falltime)_clk [*] (nano seconds)
------------------------------------------------------------------------------------------------------------------------------------
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Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3.4. Input Timing
------------------------------------------------------------------------------------------------------------------------------------
Table 5 - Input Timing Specifications
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
====================================================================================================================================
Minimum required data to T_setup ps Last data stable to clock
clock setup time [*] transition. See timing diagram
------------------------------------------------------------------------------------------------------------------------------------
Minimum required clock to T_hold ps Clock stable to first data
data hold time [*] transition. See timing diagram
------------------------------------------------------------------------------------------------------------------------------------
Clock - Data relationship Low speed data shall be clocked into
the MUX/CMU module on the RISING
------
edge of CLK_in
------------------------------------------------------------------------------------------------------------------------------------
[*]
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Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 7 of 15
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3.5. High Speed Data Output
------------------------------------------------------------------------------------------------------------------------------------
Table 6 -- High Speed Data Output Specifications
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
====================================================================================================================================
Output data rate [*] Gb/s (input rate) * 128
------------------------------------------------------------------------------------------------------------------------------------
Output connector [*]
------------------------------------------------------------------------------------------------------------------------------------
Output coupling [*] CML, centered at--600 (milli volts)
------------------------------------------------------------------------------------------------------------------------------------
Short Circuit Tolerance All outputs shall be able to withstand
an infinite duration short to ground
without sustaining damage.
------------------------------------------------------------------------------------------------------------------------------------
Output impedance [*] (ohm)
------------------------------------------------------------------------------------------------------------------------------------
Output return loss S22_data [*] dB 150 KHz less than or equal to F less than
-----------------------------------------
or equal to 11 GHz
------------------
------------------------------------------------------------------------------------------------------------------------------------
Output return loss S22_data [*] dB 11 GHz less than or equal to F less than
----------------------------------------
or equal to 16 GHz
------------------
------------------------------------------------------------------------------------------------------------------------------------
Data output amplitude (Volts)_data [*] (milli volts)-p
------------------------------------------------------------------------------------------------------------------------------------
Eye opening [*] (milli volts)-p Violation free for ITU-T STM-64 eye mask
scaled to 12.276 Gb/s
------------------------------------------------------------------------------------------------------------------------------------
Output rise / fall time (risetime)_data, Ps 20- 80% See timing diagram
(falltime)_data, [*] [*]
------------------------------------------------------------------------------------------------------------------------------------
Output overshoot, undershoot Ovsh_data, [*] % of (Volts) data Goal of 5%
Undrsh_data See timing diagram
------------------------------------------------------------------------------------------------------------------------------------
Output "eye" cross position Eye_cross [*] [*] % of (Volts) data See timing diagram
------------------------------------------------------------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 8 of 15
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3.6. High Speed Clock Outputs
------------------------------------------------------------------------------------------------------------------------------------
Table 7 - High Speed Clock Output Specifications
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
====================================================================================================================================
Output clock rate [*] Gb/s (input rate) * 128
------------------------------------------------------------------------------------------------------------------------------------
Output connector [*]
------------------------------------------------------------------------------------------------------------------------------------
Output coupling [*]
------------------------------------------------------------------------------------------------------------------------------------
Short Circuit Tolerance All outputs shall be able to
withstand an Infinite
duration short to ground
without sustaining damage.
------------------------------------------------------------------------------------------------------------------------------------
Output impedance [*] (ohm)
------------------------------------------------------------------------------------------------------------------------------------
Output return loss S22_clk [*] dB 12.0 GHz (less than or equal
to) F (less than or equal
to) 12.5 GHz
------------------------------------------------------------------------------------------------------------------------------------
Clk1 output amplitude volts_clk1 [*] mVp-p
------------------------------------------------------------------------------------------------------------------------------------
Output rise / fall time (rise time)_clk, (fall time)_clk [*] ps 20 - 80% See timing diagram
------------------------------------------------------------------------------------------------------------------------------------
Clock duty cycle Dcyc [*] [*] %
------------------------------------------------------------------------------------------------------------------------------------
Output overshoot, undershoot Ovsh_cl2G % of (volts)_clk1 See timing diagram
Undrsh_c12G [*] Goal of 5%
------------------------------------------------------------------------------------------------------------------------------------
3.7. Temperature Sensors
--------------------------------------------------------------------------------
Table 8 - Temperature Sensor Specifications
--------------------------------------------------------------------------------
Temp Sensor #1 [*]
--------------------------------------------------------------------------------
Temp Sensor #2 [*]
--------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 9 of 15
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3.8.High Speed Output Timing
---------------------------------------------------------------------------------------------------------------------------------
Table 9 - High Speed Output Timing Specifications
---------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
=================================================================================================================================
Clk1 to Data delay Tcd [*] [*] [*] ps TBD.C case temperature
Nominal supply voltages Over
entire population of modules
---------------------------------------------------------------------------------------------------------------------------------
Clk1 to Data delay variation Tcd_delta [*1 ps Tcd(max) - Tcd(min)
For a given unit over time
and worst case variation of
temperature and supply voltage.
All variation with temperature
must be monotonic and repeatable.
[*]
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 10 of 15
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3.9. Sub-Rate Clock Outputs
------------------------------------------------------------------------------------------------------------------------------------
Table 10 - Sub-Rate Clock Outputs
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
====================================================================================================================================
Frequency [*] MHz (Input data rate) * 8
------------------------------------------------------------------------------------------------------------------------------------
Output Coupling [*]
------------------------------------------------------------------------------------------------------------------------------------
Short Circuit Tolerance All outputs shall be able
to withstand an infinite
duration short to ground
without sustaining damage.
------------------------------------------------------------------------------------------------------------------------------------
Output Level (Volts)_c767_diff [*] (millivolts) Differential to 50(ohm)
------------------------------------------------------------------------------------------------------------------------------------
Clock rise / fall time (Rise Time)_c767/ ps 20 - 80%
(Rise Time)_c767 [*] [*]
------------------------------------------------------------------------------------------------------------------------------------
Clock duty cycle Dcyc_c767 [*] [*] % All clock outputs
------------------------------------------------------------------------------------------------------------------------------------
CLK3 to CLK3_b differential Tc767_skew ps
clock skew [*]
------------------------------------------------------------------------------------------------------------------------------------
Clock over / under shoot Ovrsh_c767 % of clock
Undrsh_c767 [*] amplitude
------------------------------------------------------------------------------------------------------------------------------------
Clock output impedance (impedence)_c767 [*] (ohm) Applies to Clk3 and Clk3_b
------------------------------------------------------------------------------------------------------------------------------------
3.10. Jitter Performance
------------------------------------------------------------------------------------------------------------------------------------
Table 11 - Jitter Specifications
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
------------------------------------------------------------------------------------------------------------------------------------
Jitter Transfer Function JTF [*] dB DC to 10 KHz
------------------------------------------------------------------------------------------------------------------------------------
Jitter Generation JGEN [*] mUlp-p 50 KHz to 80 MHz
Measurement technique - TBD
---
------------------------------------------------------------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 11 of 15
Issue 7
Tyco Submarine Systems, Ltd TSSL Part Number [*]
[*]
3.11. Alarm Outputs
-----------------------------------------------------------------------------------------------------------------------------------
Table 12 -- LOC1, LOC2 Output Specifications
-----------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
===================================================================================================================================
Logic HIGH level (Volt)_LOC1_(High) [*] [*] [*] (millivolts) CMOS compatible
(Volt)_L0C2_(High)
(Volt)_LOC3_(High)
-----------------------------------------------------------------------------------------------------------------------------------
Logic LOW level (Volt)_LOC1_(Low) (millivolts) CMOS compatible
(Volt)_LOC2_(Low) [*] [*]
(Volt)_LOC3_(Low)
-----------------------------------------------------------------------------------------------------------------------------------
Short Circuit Tolerance The LOC outputs shall be
able to withstand an
infinite duration short to
ground without sustaining
damage.
-----------------------------------------------------------------------------------------------------------------------------------
Clk_in level for LOC1 activate [*] (millivolts)p-p Differential
-----------------------------------------------------------------------------------------------------------------------------------
Cik_in level for LOC1 disable [*] (millivolts)p-p Differential
-----------------------------------------------------------------------------------------------------------------------------------
Activate / disable conditions Internal threshold based on
for LOC2 status of 767.3 MHz VCO output
-----------------------------------------------------------------------------------------------------------------------------------
Frequency error for activation ppm 128:16 MUX PLL out of lock
of LOC3 [*] condition
-----------------------------------------------------------------------------------------------------------------------------------
▇▇▇▇, ▇▇▇▇, ▇▇▇▇ activate / T_LOC1,
disable time T_LOC2, [*] (micro)s Alarms are active HIGH
T_LOC3
-----------------------------------------------------------------------------------------------------------------------------------
3.12. Miscellaneous
-----------------------------------------------------------------------------------------------------------------------------------
Table 13 -- Miscellaneous Specifications
-----------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
===================================================================================================================================
Lifetime [*] Years
-----------------------------------------------------------------------------------------------------------------------------------
Failure Rate [*] FIT FIT = Failures in 10/9/ hours
-----------------------------------------------------------------------------------------------------------------------------------
Environmental Requirements [*] Supplied by TSSL Exceptions
granted on case by case basis.
-----------------------------------------------------------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 12 of 15
Tyco Submarine Systems, Ltd Issue 7
TSSL Part Number [*]
[*]
4. Mechanical Requirements
4.1 Module I/O Placement
The sub-rate clocks and all low speed signals (data, clock, control,
power) shall be connected to the module through [*]
[*]. ). Figure 4 shows a rough diagram of the module I/O layout.
For exact details, see the appropriate mechanical drawing.
[*]
[*]
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 13 of 15
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
4.2. Input Bit Ordering
The required bit order at the [*] inputs is affected by the fact that
the input bit stream is first multiplexed [*] [*]. Assuming
that the desired output bit order ( [*] ) is:
[*]
The bits shall appear at the module's low speed parallel data inputs in
the order shown in Table 13. The Clk_in and Clk_in_b signals appear in the
middle of this field between bits [*] . The layout of the module's
IC's, substrate and connector shall be such that all of the low speed data
signals are located as shown in figure 4. This assures that the required
bit order can be transported from the FEC circuitry to the MUX/CMU module
via a single layer PWB without crossovers.
Table 13 - Input Bit Ordering
----------
D000
----------
D016
----------
D032
----------
D048
----------
D064
----------
D080
----------
D096
----------
D112
----------
D001
----------
D017
----------
D033
----------
D049
----------
D065
----------
D081
----------
D097
----------
D113
----------
D002
----------
----
----------
D003
----------
----
----------
D004
----------
----
----------
D005
----------
----
----------
D006
----------
----
----------
D007
----------
----
----------
D119
----------
Clk_in_b
----------
Clk_in
----------
D008
----------
----
----------
D009
----------
----
----------
D010
----------
----
----------
D011
----------
----
----------
D012
----------
----
----------
D013
----------
----
----------
D014
----------
----
----------
D015
----------
D031
----------
D047
----------
D063
----------
D079
----------
D095
----------
D111
----------
D127
----------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 14 of 15
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
4.3. Thermal Management
The primary heat removal method shall be conduction through the module's
bottom plate that will be attached to an appropriate heat sink.
4.4. Product Marking
TBD
---
5. Product Documentation
5.1. Test Results
TBD
---
5.2. Warranty Information
TBD
---
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 15 of 15
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
Component Specification for
[*]
[*]
----------------------------------
This document is TSSL Proprietary.
Use pursuant to Company instructions and applicable
Non-Disclosure Agreements
Revision History
--------------------------------------------------------------------------------
Issue # Date Author Reason for Re-issue
--------------------------------------------------------------------------------
1 [*] [*] Initial Release
--------------------------------------------------------------------------------
2 [*] [*] Spec. negotiation
--------------------------------------------------------------------------------
3 [*] [*] Spec. negotiation
--------------------------------------------------------------------------------
4 [*] [*] Module drawing update
Block diagram labeling
Vterm bypass
--------------------------------------------------------------------------------
5 [*] [*] Reduce minimum [*]
Modified specs on alarm outputs
Moved sub-rate clock outputs from SMB
connectors to parallel connector
--------------------------------------------------------------------------------
6 [*] [*] Add +5 (volts) supply
Change levels and impedance of low speed data.
Change levels and impedance of low speed clocks
Added rise/fall time for input low speed signals
Change CLK3 over/under shoot to 10%
Spec'd CLK3 output impedance
Spec'd temperature sensors
Spec'd connector type
Spec'd module thickness
--------------------------------------------------------------------------------
7 [*] [*] Removed Data_b output
Removed Clk1 output
Added LOC3 alarm
Updated supply voltages and currents
Changed levels of sub-rate clock outputs.
Removed output timing specs
General clean up.
--------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 1 of 14
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
[*]
----------------------------------------
1. General Description
1.1. This module accepts [*] each and one differential
clock at [*] . It performs the following functions:
. Uses the input clock as reference to synthesize a [*] clock
. Multiplexes the input data [*]
[*]
. Uses the [*]
[*]
. Multiplexes the internal rails [*] signal
1.2. The module produces the following output signals:
. [*] output signal
. [*] differential sub-rate clock
. [*] alarm signals
2. Block Diagram and I/O Definitions
[*]
[*]
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 2 of 14
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
--------------------------------------------------------------------------------
Table 1 - I/O Signal Descriptions
Signal Description
D\\QOO\\ - D\\127\\ [*] input data
(volts)th_data Input data threshold adjustment
Clk_in, Clk_in_b Differential [*] input clock
(volts)cc1 DC power supply
(volts)cc2 DC power supply
(volts)ee1 DC power supply
(volts)ee2 DC power supply
Data Differential [*] output signal
Clk3, Clk_b Differential [*] sub-rate clock
LOC1 Loss of input reference clock alarm - active high
LOC2 Loss of [*] VCO output alarm - active high
LOC3 Loss of PLL lock in [*] alarm - active high
(volts)term_clk Clock input termination voltage
--------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 3 of 14
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3. Module Specifications
3.1. DC Power
--------------------------------------------------------------------------------------------------------------------------
Table 2 - DC Power Specifications
--------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
==========================================================================================================================
Power Dissipation Pdisp [*] [*] ▇▇▇▇▇
--------------------------------------------------------------------------------------------------------------------------
Supply Voltages Vcc1 [*] [*] [*] Volts +7%
-
Vcc2 [*] [*] [*] Volts +7%
-
Vee1 [*] [*] [*] Volts +7%
-
Vee2 [*] [*] [*] Volts +5%
-
--------------------------------------------------------------------------------------------------------------------------
Current Draw Icc1 [*] milliAmps
Icc2 [*] milliAmps
Iee1 [*] milliAmps
Iee2 [*] milliAmps
--------------------------------------------------------------------------------------------------------------------------
Power Supply Sequencing Module shall be insensitive to supply
power-up and power-down sequencing
or timing.
--------------------------------------------------------------------------------------------------------------------------
Power Failure Tolerance Failure of one or more supplies will
not cause damage to module.
--------------------------------------------------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 4 of 14
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3.2. Data Inputs
-------------------------------------------------------------------------------------------------------------------------------
Table 3 - Data Receiver Specifications
-------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
===============================================================================================================================
Input data rate [*] [*] [*] Mb/s 128 Parallel channels
-------------------------------------------------------------------------------------------------------------------------------
Input impedance (impedence)_data [*] (kiloohm) Both to ground and Vth
-------------------------------------------------------------------------------------------------------------------------------
Input decision threshold (volts)th_data [*] [*] (millivolts) Set by Vth input
-------------------------------------------------------------------------------------------------------------------------------
Vth input impedance (impedence)_th [*] (kiloohm) Both to ground and data inputs
-------------------------------------------------------------------------------------------------------------------------------
Vth high end cutoff F_high_Vth [*] Hz 3 dB down
-------------------------------------------------------------------------------------------------------------------------------
Data input logic LOW
threshold (impedence)_data_L [*] (millivolts)
-------------------------------------------------------------------------------------------------------------------------------
Data input logic HIGH
threshold (impedance)_data_H [*] (millivolts)
-------------------------------------------------------------------------------------------------------------------------------
Input data levels [*] [*] (millivolts) each input to ground
-------------------------------------------------------------------------------------------------------------------------------
Input data rise/fall times (risetime)_data, [*] (nanoseconds)
(fulltime)_data
-------------------------------------------------------------------------------------------------------------------------------
Data transmission line (impedence)_data [*] (ohm)
impedance on module
-------------------------------------------------------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 5 of 14
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3.3. Clock inputs
---------------------------------------------------------------------------------------------------------------------------------
Table 4- Clock Receiver Specifications
---------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol MIN Typ Max Units Comments
=================================================================================================================================
Input clock rate [*] [*] [*] (Mega hertz)
---------------------------------------------------------------------------------------------------------------------------------
Input impedance (impedence)_clk [*] (ohm) Each input measured to Vterm _clk
---------------------------------------------------------------------------------------------------------------------------------
Differential input impedance (impedence)_clk_diff [*] (Kilo ohm)
---------------------------------------------------------------------------------------------------------------------------------
Clock HIGH level ("PECL") (volts)_clk_high [*] [*] (milli volts) Each input to ground
---------------------------------------------------------------------------------------------------------------------------------
Clock LOW level ("PECL") (volts)_clk_low [*] [*] (milli volts) Each input to ground
---------------------------------------------------------------------------------------------------------------------------------
Input clock over/ under shoot [*] %
---------------------------------------------------------------------------------------------------------------------------------
Clock termination voltage (Volt)sterm_clk [*] [*] [*] (milli volts) General off-module and applied
to Vterm_clk input
---------------------------------------------------------------------------------------------------------------------------------
Input clock rise/fall times (Risetime)_clk,
(fulltime)_clk [*] (nano seconds)
---------------------------------------------------------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSI PROPRIETARY Sheet 6 of 14
1/19/2000
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3.4. Input Timing
--------------------------------------------------------------------------------------------------------------------------
Table 5 - Input Timing Specifications
--------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
==========================================================================================================================
Minimum required data to T_setup [*] ps Last data stable to clock transition.
clock setup time See timing diagram
--------------------------------------------------------------------------------------------------------------------------
Minimum required clock to T_hold [*] ps Clock stable to First data
data hold time transition. See timing diagram
--------------------------------------------------------------------------------------------------------------------------
Clock - Data relationship Low speed data shall be clocked into
the MUX/CMU module on the RISING edge
------
of CLK_in
--------------------------------------------------------------------------------------------------------------------------
[*]
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 7 of 14
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3.5. High Speed Data Output
-----------------------------------------------------------------------------------------------------------------------------------
Table 6 -- High Speed Data Output Specifications
-----------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
-----------------------------------------------------------------------------------------------------------------------------------
Output data rate [*] Gb/s (input rate)* 128
-----------------------------------------------------------------------------------------------------------------------------------
Output connector [*]
-----------------------------------------------------------------------------------------------------------------------------------
Output coupling [*] CML, centered at -600 m(Volts)
-----------------------------------------------------------------------------------------------------------------------------------
Short Circuit Tolerance All outputs shall be able to withstand
an infinite duration short to ground
without sustaining damage.
-----------------------------------------------------------------------------------------------------------------------------------
Output impedance [*] (ohm)
-----------------------------------------------------------------------------------------------------------------------------------
Output return loss S22_data [*] dB ▇▇▇ ▇▇▇ ** F ** 10.0 GHz
-----------------------------------------------------------------------------------------------------------------------------------
Output return loss S22_data [*] dB 10.0 GHz ** F ** 16 GHz
-----------------------------------------------------------------------------------------------------------------------------------
Data output amplitude (Volts)_data [*] [*] (millivolts)p-p
-----------------------------------------------------------------------------------------------------------------------------------
Data eye opening [*] (millivolts)p-p Violation free for ITU-T STM-64 eye mask
-----------------------------------------------------------------------------------------------------------------------------------
Output rise / fall time (rise time)_data, [*] ps 20-80% See timing diagram
(fall time)_data
-----------------------------------------------------------------------------------------------------------------------------------
Output overshoot, undershoot Ovsh_data, [*] % of (Volts)_data See timing diagram
Undrsh_data
-----------------------------------------------------------------------------------------------------------------------------------
Output "eye" cross position Eye_cross [*] [*] % of (Volts)_data See timing diagram
-----------------------------------------------------------------------------------------------------------------------------------
** = (less than or equals to)
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
TSSL PROPRIETARY
Issue 7
1/19/2000 Sheet 8 of 14
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3.6. Temperature Sensors
--------------------------------------------------------------------------------
Table 7 -- Temperature Sensor Specifications
--------------------------------------------------------------------------------
Temp Sensor #1 [*]
--------------------------------------------------------------------------------
Temp Sensor #2 [*]
--------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
TSSL PROPRIETARY
Issue 7
1/19/2000 Sheet 9 of 14
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3.7. Sub-Rate Clock Outputs
------------------------------------------------------------------------------------------------------------------------------------
Table 8- Sub-Rate Clock Outputs
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
------------------------------------------------------------------------------------------------------------------------------------
Frequency [*] (mega hertz) (Input data rate) 8
------------------------------------------------------------------------------------------------------------------------------------
Output Coupling [*]
------------------------------------------------------------------------------------------------------------------------------------
Short Circuit Tolerance All outputs shall be able to
withstand an infinite duration
short to ground without
sustaining damage.
------------------------------------------------------------------------------------------------------------------------------------
Output Level volts_c622_diff [*] (milli volts) Differential to 50 (ohm)
------------------------------------------------------------------------------------------------------------------------------------
Clock rise/fall time rise time_c622/ [*] [*] ps 20-80%
fall time_c622
------------------------------------------------------------------------------------------------------------------------------------
Clock duty cycle Dcyc_c622 [*] [*] % All clock outputs
------------------------------------------------------------------------------------------------------------------------------------
CLK3 to CLK3_b differential Tc622_skew [*] ps
clock skew
------------------------------------------------------------------------------------------------------------------------------------
Clock over/under shoot Ovrsh_c622 [*] % of clock Applies to Clk3 and Clk3_b
Undrsh_c622 amplitude Goal of 5%
------------------------------------------------------------------------------------------------------------------------------------
Clock output impedance Impedence_c767 [*] (ohm) Applies to Clk3 and Clk3_b
------------------------------------------------------------------------------------------------------------------------------------
3.8. Jitter Performance
------------------------------------------------------------------------------------------------------------------------------------
Table 9- Jitter Specifications
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
------------------------------------------------------------------------------------------------------------------------------------
Jitter Transfer Function JTF [*] dB DC to 10 (Kilo hertz)
------------------------------------------------------------------------------------------------------------------------------------
Jitter Generation JGEN [*] mUlp-p 50 (Kilo hertz) to 80 (Mega
hertz Measurement technique-
TBD
----
------------------------------------------------------------------------------------------------------------------------------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
TSSI PROPRIETARY
Issue 7
1/19/2000 Sheet 10 of 14
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
3.9. Alarm Outputs
------------------------------------------------------------------------------------------------------------------------------------
Table 10- LOC1, LOC2 Output Specifications
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
====================================================================================================================================
Logic HIGH level volts_LOC1_High (millivolts) CMOS compatible
volts_LOC2_High [*] [*] [*]
volts_LOC3_High
------------------------------------------------------------------------------------------------------------------------------------
Logic LOW level volts_LOC1_Low (millivolts) CMOS compatible
volts_LOC2_Low [*] [*]
volts_LOC3_Low
------------------------------------------------------------------------------------------------------------------------------------
Short Circuit Tolerance The LOC outputs shall be able to
withstand an infinite duration short
to ground without sustaining damage.
------------------------------------------------------------------------------------------------------------------------------------
Clk_in level for LOC1 activate [*] (millivolts)p-p Differential
------------------------------------------------------------------------------------------------------------------------------------
Clk_in level for LOC1 disable [*] (millivolts)p-p Differential
------------------------------------------------------------------------------------------------------------------------------------
Activate / disable conditions Internal threshold based on status
for LOC2 of 622.08 (Mega hertz) VCO output
------------------------------------------------------------------------------------------------------------------------------------
Frequency error for activation
of LOC3 [*] ppm 128:16 MUX PLL out of lock condition
------------------------------------------------------------------------------------------------------------------------------------
▇▇▇▇, ▇▇▇▇, ▇▇▇▇ activate/ T_LOC1, (mirco seconds) Alarms are active HIGH
disable time T_LOC2 [*]
T_LOC3
------------------------------------------------------------------------------------------------------------------------------------
3.10 Miscellaneous
------------------------------------------------------------------------------------------------------------------------------------
Table 11- Miscellaneous Specifications
------------------------------------------------------------------------------------------------------------------------------------
Parameter Symbol Min Typ Max Units Comments
------------------------------------------------------------------------------------------------------------------------------------
Lifetime [*] Years
------------------------------------------------------------------------------------------------------------------------------------
Failure Rate [*] FIT FIT= Failures in 10//9// hours
------------------------------------------------------------------------------------------------------------------------------------
Environmental Requirements [*] Supplied by TSSL Exceptions granted
on case by case basis.
------------------------------------------------------------------------------------------------------------------------------------
Confidential material omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
TSSL PROPRIETARY
Issue 7
1/19/2000 Sheet 11 of 14
Issue 7
Tyco Submarine Systems, Ltd TSSL Part Number [*]
[*]
4. Mechanical Requirements
4.1. Module I/O Placement
The sub-rate clocks and all low speed signals (data, clock, control,
power) shall be connected to the module through [*]
[*] ). Figure 4 shows a rough diagram of the module I/O layout.
For exact details, see the appropriate mechanical drawing.
[*]
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 12 of 14
Issue 7
Tyco Submarine Systems, Ltd TSSL Part Number [*]
[*]
4.2. Input Bit Ordering
The required bit order at the [*] inputs is affected by the fact
that
[*] [*] . Assuming that the desired output bit order (at [*]
)
is: [*]
The bits shall appear at the module's low speed parallel data inputs in the
order shown in Table 13. The Clk_in and Clk_in_b signals appear in the
middle of this field between bits D\\119\\ and D\\008\\. The layout of the
module's IC's, substrate and connector shall be such that all of the low
speed data signals are located as shown in figure 4. This assures that the
required bit order can be transported from the FEC circuitry to the MUX/CMU
module via a single layer PWB without crossovers.
Table 13 -- Input Bit Ordering
-----------------
D000
-----------------
D016
-----------------
D032
-----------------
D048
-----------------
D064
-----------------
D080
-----------------
D096
-----------------
D112
-----------------
D001
-----------------
D017
-----------------
D033
-----------------
D049
-----------------
D065
-----------------
D081
-----------------
D097
-----------------
D113
-----------------
D002
-----------------
----
-----------------
D003
-----------------
----
-----------------
D004
-----------------
----
-----------------
D005
-----------------
----
-----------------
D006
-----------------
----
-----------------
D007
-----------------
----
-----------------
D119
-----------------
Clk_in_b
-----------------
Clk_in
-----------------
D008
-----------------
----
-----------------
D009
-----------------
----
-----------------
D010
-----------------
----
-----------------
D011
-----------------
----
-----------------
D012
-----------------
----
-----------------
D013
-----------------
----
-----------------
D014
-----------------
----
-----------------
D015
-----------------
D031
-----------------
D047
-----------------
D063
-----------------
D079
-----------------
D095
-----------------
D111
-----------------
D127
-----------------
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 13 of 14
Tyco Submarine Systems, Ltd Issue 7
[*] TSSL Part Number [*]
4.3. Thermal Management
The primary heat removal method shall be conduction through the
module's base plate (non-component side) that will be attached to an
appropriate heat sink.
4.4. Product Marking
TBD
---
5. Product Documentation
5.1. Test Results
TBD
---
5.2. Warranty Information
TBD
---
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.
Issue 7 TSSL PROPRIETARY
1/19/2000 Sheet 14 of 14
EXHIBIT C
SCHEDULE
AGREEMENT
[*]
Confidential materials omitted and filed separately with the Securities and
Exchange Commission. Asterisks denote omissions.