Hardware Signaling Pin Timing Requirements Clause Samples

Hardware Signaling Pin Timing Requirements. Per specifications given in Ref.[2] 2 The MSA recommends host termination resistor value of 560 Ohms, which provides the best balance of performance for both open-drain and active tri-state driver in the module. Host termination resistor values below 560Ohms are allowed, to a minimum of 250 Ohms, but this degrades active driver performance. Host termination resistor values above 560 Ohms are allowed but this degrades open-drain driver performance. The above drawings, with maximum host load capacitance of 200pF, also define the measurement set-up for module MDC timing verification. The capacitor in the drawing indicates the stray capacitance on the line. Don’t put any physical capacitor on the line. The CFP4 module utilizes MDIO IEEE Std 802.3TM-2012 clause 45 [8] for its management interface. The CFP4 MDIO implementation is defined in a separate document entitled, “CFP MSA Management Interface Specification” [3]. When multiple CFP4 modules are connected via a single bus, a particular CFP4 module can be selected by using the Physical Port Address pins.
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Hardware Signaling Pin Timing Requirements. ‌ 4 Per specifications given in Ref. [2]
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Hardware Signaling Pin Timing Requirements. Timing requirements for Hardware Signaling Pins can be found in Table 2-5. Parameter Symbol Min. Max. Unit Notes & Conditions Hardware MOD_LOPWR assert t_MOD_LOPWR_assert 1 ms Application Specific. May depend on current state condition when signal is applied. See Vendor Data Sheet Hardware MOD_LOPWR deassert t_MOD_LOPWR_deassert ms Value is dependent upon module start-up time. Please see register “Maximum High-Power-up Time” in CFP MSA Management Interface Specification [7] Receiver Loss of Signal Assert Time t_loss_assert 100 µs Maximum value designed to support telecom applications Receiver Loss of Signal De-Assert Time t_loss_deassert 100 µs Maximum value designed to support telecom applications Global Alarm Assert Delay Time GLB_ALRMn_assert 150 ms This is a logical "OR" of associated MDIO alarm & status registers. Please see CFP MSA Management Interface Specification [7] for further details Global Alarm De-Assert Delay Time GLB_ALRMn_deassert 150 ms This is a logical "OR" of associated MDIO alarm & status registers. Please see CFP MSA Management Interface Specification [7] for further details Management Interface Clock Period t_prd 250 ns MDC is 4 MHz or less Host MDIO t_setup t_setup 10 ns Host MDIO t_hold t_hold 10 ns CFP MDIO t_delay t_delay 0 175 ns Initialization time from Reset t_initialize 2.5 s Transmitter Disabled (TX_DIS asserted) t_deassert 100 µs Application Specific Transmitter Enabled (TX_DIS de-asserted) t_assert 20 ms From TX-Off state.
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Hardware Signaling Pin Timing Requirements. ‌ 3 MODULE MANAGEMENT INTERFACE DESCRIPTION‌
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Hardware Signaling Pin Timing Requirements 
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