Common use of Interrupt Clause in Contracts

Interrupt. The Host Controller processes one interrupt Endpoint Descriptor list every frame. The lower five bits of the current frame number is used as an index into an array of 32 interrupt Endpoint Descriptor lists found in the HCCA. This means each list is revisited once every 32 ms. Host Controller Driver utilizes the Host Controller algorithm to provide flexible interrupt transfer scheduling. Host Controller Driver sets up the interrupt lists to visit any given Endpoint Descriptor in as many interrupt lists as necessary to provide the interrupt granularity required for that endpoint. For example, Figure 5-4 shows the 32 interrupts lists, with 63 Endpoint Descriptors where 1 Endpoint Descriptor is visited every frame, 2 Endpoint Descriptors are visited once every 2 frames, until finally 32 different Endpoint Descriptors are visited once every 32 frames. 1 endpoint descriptor for 1ms scheduling 2 endpoint descriptors for 2ms scheduling 4 endpoint descriptors for 4ms scheduling 8 endpoint descriptors for 8ms scheduling 16 endpoint descriptors for 16ms scheduling 32 interrupt head pointers in HCCA for 32ms scheduling An important point of this list structure is that an endpoint may be pointed to by more than one preceding endpoint. In the sample Endpoint Descriptor definition, Endpoint Descriptors are tracked by Host Controller Driver with a doubly-linked list which has only one back pointer. This is implemented by building the interrupt Endpoint Descriptor list shown in Figure 5-4 at Host Controller Driver initialization time with disabled Endpoint Descriptors. These disabled descriptors are used to populate the tree and are static. This implementation is used here to simplify the sample code; it is possible to implement the interrupt lists without the statically disabled Endpoint Descriptors if the Host Controller Driver maintains multiple backward links for each Endpoint Descriptor. As illustrated in Figure 5-5, this gives Host Controller Driver 63 different scheduling lists into which it can schedule active Endpoint Descriptors. And since the disabled Endpoint Descriptors are static, Host Controller Driver can maintain this with a doubly- linked list. 00 18 04 14 0C 1C 02 12 0A 1A 06 16 0E 1E 01 11 09 05 15 0D 1D 03 13 0B 1B 07 17 0F 1F - statically disable endpoint descriptor - active endpoint descriptor 32ms 16ms 8ms 4ms 2ms 1ms HCCA Interrupt List The head of each scheduling list is either the static entry for that list or one of the 32 list heads in the HCCA area. This initialization is accomplished as follows: VOID InitailizeInterruptLists ( IN PHCD_DEVICE_DATA DeviceData ) { PHC_ENDPOINT_DESCRIPTOR ED, StaticED[ED_INTERRUPT_32ms]; ULONG i, j, k; static UCHAR Balance[16] = {0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE, 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF}; // // Allocate satirically disabled EDs, and set head pointers for scheduling lists // for (i=0; i < ED_INTERRUPT_32ms; i+) { ED = AllocateEndpointDescriptor (DeviceData); ED->PhysicalAddress = PhysicalAddressOf(&ED->HcED); DeviceData->EDList[i].PhysicalHead = &ED->HcED.NextED; ED->HcED.Control |= sKip; // mark ED as disabled InitializeListHead (&DeviceData->EDList[i].Head); StaticED[i] = ED; if (i > 0) { DeviceData->EDList[i].Next = (i-1)/2; ED->HcED.NextED = StaticED[(i-1)/2]->PhysicalAddress; } else { DeviceData->EDList[i].Next = ED_EOF; ED->HcEd.NextED = 0; } // // Set head pointers for 32ms scheduling lists which start from HCCA // for (i=0, j=ED_INTERRUPT_32ms, i<32; i++, j++) { DeviceData->EDList[j].PhysicalHead = &DeviceData->HCCA->InterruptList[i]; InitializeListHead (&DeviceData->EDList[j].Head);

Interrupt. The Host Controller processes one interrupt Endpoint Descriptor list every frame. The lower five bits of the current frame number is used as an index into an array of 32 interrupt Endpoint Descriptor lists found in the HCCA. This means each list is revisited once every 32 ms. Host Controller Driver utilizes the Host Controller algorithm to provide flexible interrupt transfer scheduling. Host Controller Driver sets up the interrupt lists to visit any given Endpoint Descriptor in as many interrupt lists as necessary to provide the interrupt granularity required for that endpoint. For example, Figure 5-4 shows the 32 interrupts lists, with 63 Endpoint Descriptors where 1 Endpoint Descriptor is visited every frame, 2 Endpoint Descriptors are visited once every 2 frames, until finally 32 different Endpoint Descriptors are visited once every 32 frames. 1 endpoint descriptor for 1ms scheduling 2 endpoint descriptors for 2ms scheduling 4 endpoint descriptors for 4ms scheduling 8 endpoint descriptors for 8ms scheduling 16 endpoint descriptors for 16ms scheduling 32 interrupt head pointers in HCCA for 32ms scheduling An important point of this list structure is that an endpoint may be pointed to by more than one preceding endpoint. In the sample Endpoint Descriptor definition, Endpoint Descriptors are tracked by Host Controller Driver with a doubly-linked list which has only one back pointer. This is implemented by building the interrupt Endpoint Descriptor list shown in Figure 5-4 at Host Controller Driver initialization time with disabled Endpoint Descriptors. These disabled descriptors are used to populate the tree and are static. This implementation is used here to simplify the sample code; it is possible to implement the interrupt lists without the statically disabled Endpoint Descriptors if the Host Controller Driver maintains multiple backward links for each Endpoint Descriptor. As illustrated in Figure 5-5, this gives Host Controller Driver 63 different scheduling lists into which it can schedule active Endpoint Descriptors. And since the disabled Endpoint Descriptors are static, Host Controller Driver can maintain this with a doubly- doubly-linked list. 00 18 04 14 0C 1C 02 12 0A 1A 06 16 0E 1E 01 11 09 05 15 0D 1D 03 13 0B 1B 07 17 0F 1F - statically disable endpoint descriptor - active endpoint descriptor 32ms 16ms 8ms 4ms 2ms 1ms HCCA Interrupt List The head of each scheduling list is either the static entry for that list or one of the 32 list heads in the HCCA area. This initialization is accomplished as follows: VOID InitailizeInterruptLists ( IN PHCD_DEVICE_DATA DeviceData ) { PHC_ENDPOINT_DESCRIPTOR ED, StaticED[ED_INTERRUPT_32ms]; ULONG i, j, k; static UCHAR Balance[16] = {0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE, 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF}; // // Allocate satirically disabled EDs, and set head pointers for scheduling lists // for (i=0; i < ED_INTERRUPT_32ms; i+) { ED = AllocateEndpointDescriptor (DeviceData); ED->PhysicalAddress = PhysicalAddressOf(&ED->HcED); DeviceData->EDList[i].PhysicalHead = &ED->HcED.NextED; ED->HcED.Control |= sKip; // mark ED as disabled InitializeListHead (&DeviceData->EDList[i].Head); StaticED[i] = ED; if (i > 0) { DeviceData->EDList[i].Next = (i-1)/2; ED->HcED.NextED = StaticED[(i-1)/2]->PhysicalAddress; } else { DeviceData->EDList[i].Next = ED_EOF; ED->HcEd.NextED = 0; } // // Set head pointers for 32ms scheduling lists which start from HCCA // for (i=0, j=ED_INTERRUPT_32ms, i<32; i++, j++) { DeviceData->EDList[j].PhysicalHead = &DeviceData->HCCA->InterruptList[i]; InitializeListHead (&DeviceData->EDList[j].Head);